| Message ID | 1484864995-10679-2-git-send-email-javier@osg.samsung.com (mailing list archive) |
|---|---|
| State | Rejected |
| Headers | show |
On Thu, Jan 19, 2017 at 07:29:55PM -0300, Javier Martinez Canillas wrote: > Commit 94aed538e032 ("ARM: dts: exynos: Add async-bridge clock to MFC > power domain for Exynos5420") fixed an imprecise external abort error > when the MFC registers were tried to be accessed and the needed clock > for the asynchronous bridges were gated. > > But according to the Exynos5420 manual the "Gating AXI clock for MFC" > is not CLK_ACLK333 but CLK_MFC. > > The end effect is the same because CLK_ACLK333 is a parent of CLK_MFC > but the correct clock should be used instead. > > Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> > > --- > > arch/arm/boot/dts/exynos5420.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Is this still needed? Best regards, Krzysztof > > diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi > index 906a1a42a7ea..ffb148ea91d6 100644 > --- a/arch/arm/boot/dts/exynos5420.dtsi > +++ b/arch/arm/boot/dts/exynos5420.dtsi > @@ -294,7 +294,7 @@ > reg = <0x10044060 0x20>; > clocks = <&clock CLK_FIN_PLL>, > <&clock CLK_MOUT_USER_ACLK333>, > - <&clock CLK_ACLK333>; > + <&clock CLK_MFC>; > clock-names = "oscclk", "clk0","asb0"; > #power-domain-cells = <0>; > }; > -- > 2.7.4 > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hello Krzysztof, On 01/20/2017 01:28 PM, Krzysztof Kozlowski wrote: > On Thu, Jan 19, 2017 at 07:29:55PM -0300, Javier Martinez Canillas wrote: >> Commit 94aed538e032 ("ARM: dts: exynos: Add async-bridge clock to MFC >> power domain for Exynos5420") fixed an imprecise external abort error >> when the MFC registers were tried to be accessed and the needed clock >> for the asynchronous bridges were gated. >> >> But according to the Exynos5420 manual the "Gating AXI clock for MFC" >> is not CLK_ACLK333 but CLK_MFC. >> >> The end effect is the same because CLK_ACLK333 is a parent of CLK_MFC >> but the correct clock should be used instead. >> >> Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> >> >> --- >> >> arch/arm/boot/dts/exynos5420.dtsi | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) > > Is this still needed? > Not really, only if we care about correctness in the existing power domains that have their clocks defined. But as said, even currently with CLK_ACLK333 works due to the clock hierarchy. I think is less of an issue now that we prefer to mark clocks that needs to be ungated as critical instead of growing the DT ABI. > Best regards, > Krzysztof > Best regards,
On Fri, Jan 20, 2017 at 02:15:40PM -0300, Javier Martinez Canillas wrote: > Hello Krzysztof, > > On 01/20/2017 01:28 PM, Krzysztof Kozlowski wrote: > > On Thu, Jan 19, 2017 at 07:29:55PM -0300, Javier Martinez Canillas wrote: > >> Commit 94aed538e032 ("ARM: dts: exynos: Add async-bridge clock to MFC > >> power domain for Exynos5420") fixed an imprecise external abort error > >> when the MFC registers were tried to be accessed and the needed clock > >> for the asynchronous bridges were gated. > >> > >> But according to the Exynos5420 manual the "Gating AXI clock for MFC" > >> is not CLK_ACLK333 but CLK_MFC. > >> > >> The end effect is the same because CLK_ACLK333 is a parent of CLK_MFC > >> but the correct clock should be used instead. > >> > >> Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> > >> > >> --- > >> > >> arch/arm/boot/dts/exynos5420.dtsi | 2 +- > >> 1 file changed, 1 insertion(+), 1 deletion(-) > > > > Is this still needed? > > > > Not really, only if we care about correctness in the existing power domains > that have their clocks defined. But as said, even currently with CLK_ACLK333 > works due to the clock hierarchy. > > I think is less of an issue now that we prefer to mark clocks that needs to > be ungated as critical instead of growing the DT ABI. Okay then, I'll skip the patch. Resend if it turns out to be needed. Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 906a1a42a7ea..ffb148ea91d6 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -294,7 +294,7 @@ reg = <0x10044060 0x20>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>, - <&clock CLK_ACLK333>; + <&clock CLK_MFC>; clock-names = "oscclk", "clk0","asb0"; #power-domain-cells = <0>; };
Commit 94aed538e032 ("ARM: dts: exynos: Add async-bridge clock to MFC power domain for Exynos5420") fixed an imprecise external abort error when the MFC registers were tried to be accessed and the needed clock for the asynchronous bridges were gated. But according to the Exynos5420 manual the "Gating AXI clock for MFC" is not CLK_ACLK333 but CLK_MFC. The end effect is the same because CLK_ACLK333 is a parent of CLK_MFC but the correct clock should be used instead. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> --- arch/arm/boot/dts/exynos5420.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)