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Wed, 25 Jan 2017 11:51:05 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20170125115104eucas1p1c725f2854fb4cff98548721f79dd6a5b~dAXd3akbu1025310253eucas1p1k; Wed, 25 Jan 2017 11:51:04 +0000 (GMT) X-AuditID: cbfec7f5-f79d06d000004445-70-58889129fb3d Received: from eusync3.samsung.com ( [203.254.199.213]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 49.8E.10233.52198885; Wed, 25 Jan 2017 11:51:01 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OKC00H7J3KW4970@eusync3.samsung.com>; Wed, 25 Jan 2017 11:51:04 +0000 (GMT) From: Marek Szyprowski To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , Lee Jones , Bartlomiej Zolnierkiewicz Subject: [PATCH 6/7] mfd: exynos-lpass: Add support for clocks Date: Wed, 25 Jan 2017 12:50:30 +0100 Message-id: <1485345031-2948-7-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1485345031-2948-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrEIsWRmVeSWpSXmKPExsWy7djPc7qaEzsiDHpWsFlsnLGe1eL8+Q3s Fve/HmW0mPJnOZPFpsfXWC02z//DaHF51xw2ixnn9zFZrD1yl93i8Jt2VotVu/4wOnB77Jx1 l91j06pONo871/aweWxeUu/Rt2UVo8fnTXIBbFFcNimpOZllqUX6dglcGe/er2EruCJd0XB5 K1MD412xLkZODgkBE4mT3R3MELaYxIV769m6GLk4hASWMkq8bDzFDOF8ZpSYevMYO0zH3IXn oBLLGCW6n1xhgXAamCTWvdvKCFLFJmAo0fW2C2yWiEA7o8Tdvg4mEIdZYBOTRNuSE2AbhQXs JN78fsUGYrMIqEo8m7oJrJtXwF1ib/MFRoh9chInj01m7WLk4OAU8JA48sYEZI6EwHR2iW0X ljOCxCUEZCU2HYB6wkWi+3wLlC0s8er4FqizZSQuT+5mgbD7GSWaWrUh7BmMEufe8kLY1hKH j19kBbGZBfgkJm2bzgwxnleio00IosRD4tn+Y0wQtqPEicen2SGen80o0bnvJ/MERpkFjAyr GEVSS4tz01OLTfWKE3OLS/PS9ZLzczcxAmP+9L/jX3cwLj1mdYhRgINRiYd3QlJ7hBBrYllx Ze4hRgkOZiURXoeWjggh3pTEyqrUovz4otKc1OJDjNIcLErivHsWXAkXEkhPLEnNTk0tSC2C yTJxcEo1MDKsv9QkNud5wd9buYUOt85m8ooamu74m9WYYdm/40KLgURnUk2W4loF98nCcz8a b53N4p1y7+6cuvilTfOkv4QvvVD9Zqqxw+7p1qbpLgtL7v3iC3cIqZSXmNNTlb+60OeTn7Pw BRW2BaL7xPZIhji82+k1i/vhpvXTrF/Ib7WOXP7P7H5CiBJLcUaioRZzUXEiAF573c/1AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpikeLIzCtJLcpLzFFi42I5/e/4VV3ViR0RBs3dOhYbZ6xntTh/fgO7 xf2vRxktpvxZzmSx6fE1VovN8/8wWlzeNYfNYsb5fUwWa4/cZbc4/Kad1WLVrj+MDtweO2fd ZffYtKqTzePOtT1sHpuX1Hv0bVnF6PF5k1wAW5SbTUZqYkpqkUJqXnJ+SmZeuq1SaIibroWS Ql5ibqqtUoSub0iQkkJZYk4pkGdkgAYcnAPcg5X07RLcMt69X8NWcEW6ouHyVqYGxrtiXYyc HBICJhJzF55jhrDFJC7cW8/WxcjFISSwhFGi8d1JRginiUli+qtjLCBVbAKGEl1vu8CqRATa GSVe377GBOIwC2xhkujadJEdpEpYwE7ize9XbCA2i4CqxLOpmxhBbF4Bd4m9zRcYIfbJSZw8 Npm1i5GDg1PAQ+LIGxOQsBBQyZzmXuYJjLwLGBlWMYqklhbnpucWG+kVJ+YWl+al6yXn525i BIb/tmM/t+xg7HoXfIhRgINRiYd3QlJ7hBBrYllxZe4hRgkOZiURXoeWjggh3pTEyqrUovz4 otKc1OJDjKZAN01klhJNzgfGZl5JvKGJobmloZGxhYW5kZGSOO/UD1fChQTSE0tSs1NTC1KL YPqYODilGhjnTHxZbqGx0euP/npfhi117zuOzQ085PheotzD7EGdhjHLkqD72vUayQXT1A1m ebw9dL7NwmGp06Ss/mlnxScvyQqcwZN2SL3jVchj1qOP7Xh0t70qyI/WdasLbWdI8FnELHYz 58zSpaFlXQktJVmBSw6nWXEJTtMSangpEjBDo6cu5YVmlBJLcUaioRZzUXEiADdDnCCVAgAA X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170125115104eucas1p1c725f2854fb4cff98548721f79dd6a5b X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170125115104eucas1p1c725f2854fb4cff98548721f79dd6a5b X-RootMTR: 20170125115104eucas1p1c725f2854fb4cff98548721f79dd6a5b References: <1485345031-2948-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Exynos LPASS requires some clocks to be enabled to make any access to its registers. This patch adds code for handling such clocks. For current set of registers it is enough to keep sfr0_ctrl clock enabled. Till now it worked only because those clocks were enabled by bootloader and driver probe() happened before they were disabled by clock core because of lack of users. Handling those clocks is also needed to make it possible to enable support for audio power domain. Signed-off-by: Marek Szyprowski --- .../devicetree/bindings/mfd/samsung,exynos5433-lpass.txt | 6 ++++++ drivers/mfd/exynos-lpass.c | 10 ++++++++++ 2 files changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt index a8deaee82c44..df664018c148 100644 --- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt +++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt @@ -5,6 +5,10 @@ Required properties: - compatible : "samsung,exynos5433-lpass" - reg : should contain the LPASS top SFR region location and size + - clock-names : should contain following required clocks: "sfr0_ctrl" + - clocks : should contain clock specifiers of all clocks, which + input names have been specified in clock-names + property, in same order. - #address-cells : should be 1 - #size-cells : should be 1 - ranges : must be present @@ -24,6 +28,8 @@ Example: audio-subsystem { compatible = "samsung,exynos5433-lpass"; reg = <0x11400000 0x100>, <0x11500000 0x08>; + clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>; + clock-names = "sfr0_ctrl"; #address-cells = <1>; #size-cells = <1>; ranges; diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c index 17915daa2e80..44d8ea1a978b 100644 --- a/drivers/mfd/exynos-lpass.c +++ b/drivers/mfd/exynos-lpass.c @@ -14,6 +14,7 @@ * only version 2 as published by the Free Software Foundation. */ +#include #include #include #include @@ -52,6 +53,7 @@ struct exynos_lpass { /* pointer to the LPASS TOP regmap */ struct regmap *top; + struct clk *sfr0_clk; }; static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask) @@ -71,6 +73,8 @@ static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask) static void exynos_lpass_enable(struct exynos_lpass *lpass) { + clk_prepare_enable(lpass->sfr0_clk); + /* Unmask SFR, DMA and I2S interrupt */ regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S); @@ -88,6 +92,8 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass) /* Mask any unmasked IP interrupt sources */ regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0); regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0); + + clk_disable_unprepare(lpass->sfr0_clk); } static const struct regmap_config exynos_lpass_reg_conf = { @@ -114,6 +120,10 @@ static int exynos_lpass_probe(struct platform_device *pdev) if (IS_ERR(base_top)) return PTR_ERR(base_top); + lpass->sfr0_clk = clk_get(dev, "sfr0_ctrl"); + if (IS_ERR(lpass->sfr0_clk)) + return PTR_ERR(lpass->sfr0_clk); + lpass->top = regmap_init_mmio(dev, base_top, &exynos_lpass_reg_conf); if (IS_ERR(lpass->top)) {