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Wed, 25 Jan 2017 11:52:41 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20170125115241eucas1p25f7244ee4c79f42de48d91a2f659ce8c~dAY30yuZu1352813528eucas1p26; Wed, 25 Jan 2017 11:52:41 +0000 (GMT) X-AuditID: cbfec7f1-f793f6d000007796-a4-588891892370 Received: from eusync4.samsung.com ( [203.254.199.214]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id BE.CE.10233.68198885; Wed, 25 Jan 2017 11:52:38 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OKC00K703NPQX90@eusync4.samsung.com>; Wed, 25 Jan 2017 11:52:41 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi Subject: [PATCH] clk: samsung: pll: Add enable/disable support for PLL35XX clocks Date: Wed, 25 Jan 2017 12:52:32 +0100 Message-id: <1485345152-3140-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrNIsWRmVeSWpSXmKPExsWy7djP87qdEzsiDNZ2mVpsnLGe1eL6l+es FufPb2C3mHF+H5PF2iN32S0Ov2lndWDz2LSqk82jb8sqRo/Pm+QCmKO4bFJSczLLUov07RK4 Mt5s9yu4IVMx6XEfewPjTfEuRk4OCQETiQeLL7NB2GISF+6tB7K5OIQEljJKzFhwhBnC+cwo cevUQWaYjj+d19khEssYJc7sugDV0sAkMeHxSbAqNgFDia63XWBzRQRUJT63LQDrYBZ4yihx b3ELE0hCWCBY4tm8+2ANLEBFL6cfYgWxeQXcJbpmP2SHWCcncfLYZFaQZgmBA2wSVw99BZrK AeTISmw6AHWSi8SCewcZIWxhiVfHt0D1ykhcntzNAmH3M0o0tWpD2DMYJc695YWwrSUOH78I tpdZgE9i0rbpzBDjeSU62oQgTA+J5SuTIKodJc5OOc0IEhYSiJXY+pV9AqP0AkaGVYwiqaXF uempxUZ6xYm5xaV56XrJ+bmbGIFRePrf8Y87GN+fsDrEKMDBqMTD+yKlPUKINbGsuDL3EKME B7OSCK9DS0eEEG9KYmVValF+fFFpTmrxIUZpDhYlcd49C66ECwmkJ5akZqemFqQWwWSZODil GhgVZnCFin/LCI459KhqU+rc2w/veq/4JZnue1l559eStxtLvvRVRN/K+NM32fHVfta7xuIO db11u9daHslfZpIXnZvcHqBqeFjzxtnZGtF87RsSv2x3WmcxP0xjgyXPlL3urCVGV0P/r5zD ciJhd2taZKzo7W99qyqEr667uob95bbUlDnv7BcqsRRnJBpqMRcVJwIAZfwAjr4CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrELMWRmVeSWpSXmKPExsVy+t/xa7ptEzsiDLafE7bYOGM9q8X1L89Z Lc6f38BuMeP8PiaLtUfuslscftPO6sDmsWlVJ5tH35ZVjB6fN8kFMEe52WSkJqakFimk5iXn p2TmpdsqhYa46VooKeQl5qbaKkXo+oYEKSmUJeaUAnlGBmjAwTnAPVhJ3y7BLePNdr+CGzIV kx73sTcw3hTvYuTkkBAwkfjTeZ0dwhaTuHBvPVsXIxeHkMASRokpp++xQjhNTBIzz+1mBqli EzCU6HrbxQZiiwioSnxuW8AOUsQs8JxR4v3ufhaQhLBAsMSzeffBGliAil5OP8QKYvMKuEt0 zX4ItU5O4uSxyawTGLkXMDKsYhRJLS3OTc8tNtIrTswtLs1L10vOz93ECAy/bcd+btnB2PUu +BCjAAejEg/vhKT2CCHWxLLiytxDjBIczEoivA4tHRFCvCmJlVWpRfnxRaU5qcWHGE2Blk9k lhJNzgfGRl5JvKGJobmloZGxhYW5kZGSOO/UD1fChQTSE0tSs1NTC1KLYPqYODilGhi1enSz zuY+usLfceHV/c7Pd1jO8Ce+N+wPWetb/7dLk9XVJfd22lczbwY+783LF+pImkX/myZl585s v2YK+41wTZ2J/V0P3u3if7P09IS8rKqfVU09Tb8cT3TO+Zx1LbrqivOkXe2n3YOOL3aO2PrD 9WLKvc1nv0W+azO5bHbY3HTRg+Mfmn8qsRRnJBpqMRcVJwIAzGIF91UCAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170125115241eucas1p25f7244ee4c79f42de48d91a2f659ce8c X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170125115241eucas1p25f7244ee4c79f42de48d91a2f659ce8c X-RootMTR: 20170125115241eucas1p25f7244ee4c79f42de48d91a2f659ce8c References: Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some PLLs might be disabled by default after turning off and then on a power domain which they belongs to. To avoid configuring a disabled PLL, add proper code for handling PLL enable/disable. Signed-off-by: Marek Szyprowski --- This patchset is a next step to add support for all power domains on Exynos5433 SoCs. This patchset contains patches for initial clocks configuration on TM2/TM2e boards. Till now all PLLs worked only because they were enabled by the bootloader. However when power domains are added, such configuration might be lost if the display power domain get turned off before clock controller's probe. Patches have been generated on top of linux-next from 25th January 2017. This is a part of a larger task, which goal is to add support for power domains on Exynos5433 SoCs / TM2 boards. All patches needed to get it working have been pushed to the following git repo: https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd This patch was also tested on Exynos4412-based Odroid U3 board, which also uses some PLL35XX clocks. Best regards Marek Szyprowski Samsung R&D Institute Poland --- drivers/clk/samsung/clk-pll.c | 45 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 38 insertions(+), 7 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 9617825daabb..52290894857a 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -136,11 +136,39 @@ static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw, #define PLL35XX_MDIV_MASK (0x3FF) #define PLL35XX_PDIV_MASK (0x3F) #define PLL35XX_SDIV_MASK (0x7) -#define PLL35XX_LOCK_STAT_MASK (0x1) #define PLL35XX_MDIV_SHIFT (16) #define PLL35XX_PDIV_SHIFT (8) #define PLL35XX_SDIV_SHIFT (0) #define PLL35XX_LOCK_STAT_SHIFT (29) +#define PLL35XX_ENABLE_SHIFT (31) + +static int samsung_pll35xx_enable(struct clk_hw *hw) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp; + + tmp = readl_relaxed(pll->con_reg); + tmp |= BIT(PLL35XX_ENABLE_SHIFT); + writel_relaxed(tmp, pll->con_reg); + + /* wait_lock_time */ + do { + cpu_relax(); + tmp = readl_relaxed(pll->con_reg); + } while (!(tmp & BIT(PLL35XX_LOCK_STAT_SHIFT))); + + return 0; +} + +static void samsung_pll35xx_disable(struct clk_hw *hw) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp; + + tmp = readl_relaxed(pll->con_reg); + tmp &= ~BIT(PLL35XX_ENABLE_SHIFT); + writel_relaxed(tmp, pll->con_reg); +} static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) @@ -210,12 +238,13 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, (rate->sdiv << PLL35XX_SDIV_SHIFT); writel_relaxed(tmp, pll->con_reg); - /* wait_lock_time */ - do { - cpu_relax(); - tmp = readl_relaxed(pll->con_reg); - } while (!(tmp & (PLL35XX_LOCK_STAT_MASK - << PLL35XX_LOCK_STAT_SHIFT))); + /* wait_lock_time if enabled */ + if (tmp & BIT(PLL35XX_ENABLE_SHIFT)) { + do { + cpu_relax(); + tmp = readl_relaxed(pll->con_reg); + } while (!(tmp & BIT(PLL35XX_LOCK_STAT_SHIFT))); + } return 0; } @@ -223,6 +252,8 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, .recalc_rate = samsung_pll35xx_recalc_rate, .round_rate = samsung_pll_round_rate, .set_rate = samsung_pll35xx_set_rate, + .enable = samsung_pll35xx_enable, + .disable = samsung_pll35xx_disable, }; static const struct clk_ops samsung_pll35xx_clk_min_ops = {