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Thu, 26 Jan 2017 12:38:09 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20170126123806eucas1p2dfbb67c5248e6c3dd979bdd343a3b7cb~dUpz-fNwP2094220942eucas1p22; Thu, 26 Jan 2017 12:38:06 +0000 (GMT) X-AuditID: cbfec7ef-f79d26d00000420c-82-5889edb1dc7c Received: from eusync4.samsung.com ( [203.254.199.214]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id E7.58.10233.BADE9885; Thu, 26 Jan 2017 12:38:03 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OKE0099K0FDHI20@eusync4.samsung.com>; Thu, 26 Jan 2017 12:38:06 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi Subject: [PATCH v2 3/3] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e Date: Thu, 26 Jan 2017 13:37:54 +0100 Message-id: <1485434274-6579-4-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1485434274-6579-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrGIsWRmVeSWpSXmKPExsWy7djP87ob33ZGGOzZqmGxccZ6VovrX56z Wpw/v4HdYsb5fUwWa4/cZbc4/Kad1YHNY9OqTjaPvi2rGD0+b5ILYI7isklJzcksSy3St0vg yji2R6vgu0bFz9P7GRsYbyp1MXJySAiYSMycdYwZwhaTuHBvPRuILSSwjFHizatwCPszo8T9 mxEw9S3r9zLC1ZzZnQphNzBJLDobAGKzCRhKdL3tApsjIqAq8bltAXsXIxcHs8BTRol7i1uY QBLCAikSZw63gi1mASp6+2kOO4jNK+Au8aPxMTvEMjmJk8cms4LYnAIeEus+XWIDGSQhcJ9N 4vzBd0BXcAA5shKbDkA94CLxYt9CNghbWOLV8S1Qc2QkLk/uZoGw+xklmlq1IewZjBLn3vJC 2NYSh49fBNvFLMAnMWnbdGaI8bwSHW1CECUeEouWvYEa4yix9sl5sHOEBGYzSjw53sM6gVFm ASPDKkaR1NLi3PTUYkO94sTc4tK8dL3k/NxNjMDYPP3v+PsdjE+bQw4xCnAwKvHwHtjRESHE mlhWXJl7iFGCg1lJhHfhy84IId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rx7F1wJFxJITyxJzU5N LUgtgskycXBKNTCGvY+71bVimZ+a1i7W3Rp2DlvtXpw52XiV/3ZQdRr3jSnZUuxb+w4uWZau Pfl9anT4WpcyvqcJy3weRKYdSzg414XdLoiZl33Nl5/LfSYKL+iffPtsaHtr9c4bnHGTDz47 EH3vXqzm5L7uBcxHXOU+qHQve7SEV2DqVg8uV3kl+bQb3gcT/2QqsRRnJBpqMRcVJwIAL4zQ A8kCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBLMWRmVeSWpSXmKPExsVy+t/xa7qr33ZGGHxo1rbYOGM9q8X1L89Z Lc6f38BuMeP8PiaLtUfuslscftPO6sDmsWlVJ5tH35ZVjB6fN8kFMEe52WSkJqakFimk5iXn p2TmpdsqhYa46VooKeQl5qbaKkXo+oYEKSmUJeaUAnlGBmjAwTnAPVhJ3y7BLePYHq2C7xoV P0/vZ2xgvKnUxcjJISFgItGyfi8jhC0mceHeerYuRi4OIYEljBILz6xkAkkICTQxSVxvMQGx 2QQMJbredrGB2CICqhKf2xawgzQwCzxnlHi/u58FJCEskCKx/t0rsCIWoKK3n+awg9i8Au4S Pxofs0Nsk5M4eWwyK4jNKeAhse7TJaB6DqBl7hI71vJPYORdwMiwilEktbQ4Nz232EivODG3 uDQvXS85P3cTIzBUtx37uWUHY9e74EOMAhyMSjy8Gds6IoRYE8uKK3MPMUpwMCuJ8C582Rkh xJuSWFmVWpQfX1Sak1p8iNEU6KaJzFKiyfnAOMoriTc0MTS3NDQytrAwNzJSEued+uFKuJBA emJJanZqakFqEUwfEwenVAPjPJsddldW7LQ/UDnrP6968tvFxbu38XduFT25ty6qe8n5f+K8 b5h8+L//Kr2TJyGjvmPeAuVq/3pDu+Q/Ff2WpjfPrPaObvhUdZalfSLrJ/k/SdMmPdJ6F9c4 ReB54cV9NTY+Mc/uu67h+Cx2j6FG7vyeU3PL288u2TjzxaGnfEkPbz18XGyjoMRSnJFoqMVc VJwIAJZshzhrAgAA X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170126123806eucas1p2dfbb67c5248e6c3dd979bdd343a3b7cb X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170126123806eucas1p2dfbb67c5248e6c3dd979bdd343a3b7cb X-RootMTR: 20170126123806eucas1p2dfbb67c5248e6c3dd979bdd343a3b7cb References: <1485434274-6579-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add initial clock configuration for display subsystem for Exynos5433 based TM2/TM2e boards in device tree in order to avoid dependency on the configuration left by the bootloader. This initial configuration is also needed to ensure that display subsystem is operational if display power domain gets turned off before clock controller is probed and the inital clock configuration left by the bootloader saved. TM2 and TM2e uses different rate for DISP PLL clock, but for better maintainability all 'assigned-clocks-*' properties for DISP CMU are defines in each board dts instead of redefining the rates property. Signed-off-by: Marek Szyprowski --- .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 --------- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 29 ++++++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 29 ++++++++++++++++++++++ 3 files changed, 58 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 5c207575ed0a..1c1c03142e6d 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -217,18 +217,6 @@ assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>; }; -&cmu_disp { - assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, - <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; - assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, - <0>, - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; - assigned-clock-rates = <0>, <400000000>; -}; - &cmu_fsys { assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, <&cmu_top CLK_MOUT_SCLK_USBHOST30>, diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts index ddba2f889326..b8bb053495af 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts @@ -18,6 +18,35 @@ compatible = "samsung,tm2", "samsung,exynos5433"; }; +&cmu_disp { + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, + <&cmu_disp CLK_MOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; + assigned-clock-parents = <0>, <0>, + <&cmu_mif CLK_ACLK_DISP_333>, + <&cmu_mif CLK_SCLK_DSIM0_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, + <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; + assigned-clock-rates = <250000000>, <400000000>; +}; + &hsi2c_9 { status = "okay"; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts index d8bca75a1afe..c27500b7d8b5 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts @@ -18,6 +18,35 @@ compatible = "samsung,tm2e", "samsung,exynos5433"; }; +&cmu_disp { + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, + <&cmu_disp CLK_MOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; + assigned-clock-parents = <0>, <0>, + <&cmu_mif CLK_ACLK_DISP_333>, + <&cmu_mif CLK_SCLK_DSIM0_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, + <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; + assigned-clock-rates = <278000000>, <400000000>; +}; + &ldo31_reg { regulator-name = "TSP_VDD_1.8V_AP"; regulator-min-microvolt = <1800000>;