From patchwork Fri Jan 27 11:20:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 9541385 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0BC41601D7 for ; Fri, 27 Jan 2017 11:23:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EEEB520007 for ; Fri, 27 Jan 2017 11:23:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E12E3252D5; Fri, 27 Jan 2017 11:23:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6601D20007 for ; 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Fri, 27 Jan 2017 11:20:56 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20170127112056eucas1p15ced94a57821f980445c86f1393d5a94~dnPt8SQXk2992829928eucas1p1T; Fri, 27 Jan 2017 11:20:56 +0000 (GMT) X-AuditID: cbfec7f4-f79716d000006f65-2a-588b2d189b94 Received: from eusync1.samsung.com ( [203.254.199.211]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id CD.25.06687.85D2B885; Fri, 27 Jan 2017 11:22:00 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OKF00D4ZRIP80B0@eusync1.samsung.com>; Fri, 27 Jan 2017 11:20:55 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi , Andrzej Hajda Subject: [PATCH v3 3/3] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e Date: Fri, 27 Jan 2017 12:20:42 +0100 Message-id: <1485516042-32291-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <20170126193529.5dyynx5dpmtmje5b@kozik-lap> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrLIsWRmVeSWpSXmKPExsWy7djPc7oSut0RBs+fqVjcWneO1WLjjPWs Fte/PGe1OH9+A7vFjPP7mCzWHrnLbnH4TTurA7vHplWdbB59W1YxenzeJBfAHMVlk5Kak1mW WqRvl8CVsW9WE2vBT52KWR0nWBoYn6p2MXJySAiYSFx4+JIVwhaTuHBvPRuILSSwlFHi2weR LkYuIPszo8TDz7+ZYRoe/LzKBJFYxigxf9ZUFgingUni0+w9YFVsAoYSXW+7wEaJCKhKfG5b wA5SxCzQxSSx/0ojUAcHh7BAisSEr2EgNSxANVs7VrOD2LwCHhJz9/9lhNgmJ3Hy2GSw8zgF LCSe3JrBDDJHQuA+m8TSc3vB5kgIyEpsOgB1nYvE4dP3WCBsYYlXx7ewQ9gyEp0dB5kg7H5G iaZWbQh7BqPEube8ELa1xOHjF8F2MQvwSUzaNp0ZYjyvREebEESJh8S3r/sYIcKOEqt7wiBe 72aUmLdpFvsERpkFjAyrGEVSS4tz01OLTfSKE3OLS/PS9ZLzczcxAiP19L/jX3YwLj5mdYhR gINRiYeXQbYrQog1say4MvcQowQHs5IIr65Yd4QQb0piZVVqUX58UWlOavEhRmkOFiVx3j0L roQLCaQnlqRmp6YWpBbBZJk4OKUaGE3NzHzeCzCkVJz87/l4vWvr8yc9XGwfbN8Zm/o89DTw M3zUUfHq3nVpJb3FFwuOHq9ZG/2N7XTUdZVzh7Yfvul5c6L0bnWFkudxc5ctdKyeyyYTzLuz 4eyXaf0/TJ+rS329xnSLcdmGu2J75ofU63+ruKrgcOK92X6PvbdUNfkO7lzxfpapvIsSS3FG oqEWc1FxIgA00LdH0AIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrHLMWRmVeSWpSXmKPExsVy+t/xy7oRut0RBt97TSxurTvHarFxxnpW i+tfnrNanD+/gd1ixvl9TBZrj9xltzj8pp3Vgd1j06pONo++LasYPT5vkgtgjnKzyUhNTEkt UkjNS85PycxLt1UKDXHTtVBSyEvMTbVVitD1DQlSUihLzCkF8owM0ICDc4B7sJK+XYJbxr5Z TawFP3UqZnWcYGlgfKraxcjJISFgIvHg51UmCFtM4sK99WwgtpDAEkaJ2X2sXYxcQHYTk8Td l9NZQBJsAoYSXW+7wIpEBFQlPrctYAexmQV6mCS6ugVAbGGBFInpL5+B1bMA1WztWA1Wwyvg ITF3/19GiGVyEiePTWYFsTkFLCSe3JrBDLHYXGLSpZfsExh5FzAyrGIUSS0tzk3PLTbUK07M LS7NS9dLzs/dxAgM223Hfm7ewXhpY/AhRgEORiUe3gj5rggh1sSy4srcQ4wSHMxKIry6Yt0R QrwpiZVVqUX58UWlOanFhxhNgY6ayCwlmpwPjKm8knhDE0NzS0MjYwsLcyMjJXHekg9XwoUE 0hNLUrNTUwtSi2D6mDg4pRoYA/dvVa1OPhGxboOMq4fWjJ1Ja7UTvp0tiI1datby4dRju6Oz lxx7P3sD//fXGX9fSrKf0/e5p7fm29kvvJqPrTZcS9SMas2cKHRw+SyXOQ8ezmDmduh50Zk+ a+U0KZ+CtojoFSd3rN8Q8MCxxSBU39SVU1PCMX/p8k85+Qa2vd63A12Wi8h9VWIpzkg01GIu Kk4EAEOlJCFxAgAA X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170127112056eucas1p15ced94a57821f980445c86f1393d5a94 X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170127112056eucas1p15ced94a57821f980445c86f1393d5a94 X-RootMTR: 20170127112056eucas1p15ced94a57821f980445c86f1393d5a94 References: <20170126193529.5dyynx5dpmtmje5b@kozik-lap> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add initial clock configuration for display subsystem for Exynos5433 based TM2/TM2e boards in device tree in order to avoid dependency on the configuration left by the bootloader. This initial configuration is also needed to ensure that display subsystem is operational if display power domain gets turned off before clock controller is probed and the inital clock configuration left by the bootloader saved. TM2 and TM2e uses different rate for DISP PLL clock, but for better maintainability all 'assigned-clocks-*' properties for DISP CMU are defines in each board dts instead of redefining the rates property. Signed-off-by: Marek Szyprowski --- Changelog: v3: - added comment about DISP CMU clocks configuration on TM2 and TM2e --- .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 -------- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 34 ++++++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 34 ++++++++++++++++++++++ 3 files changed, 68 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 53fd0683d400..098ad557fee3 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -217,18 +217,6 @@ assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>; }; -&cmu_disp { - assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, - <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; - assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, - <0>, - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; - assigned-clock-rates = <0>, <400000000>; -}; - &cmu_fsys { assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, <&cmu_top CLK_MOUT_SCLK_USBHOST30>, diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts index 6d362f964b3a..db3fed27728b 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts @@ -18,6 +18,40 @@ compatible = "samsung,tm2", "samsung,exynos5433"; }; +&cmu_disp { + /* + * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned + * clocks properties for DISP CMU for each board to keep them together + * for easier review and maintenance. + */ + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, + <&cmu_disp CLK_MOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; + assigned-clock-parents = <0>, <0>, + <&cmu_mif CLK_ACLK_DISP_333>, + <&cmu_mif CLK_SCLK_DSIM0_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, + <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; + assigned-clock-rates = <250000000>, <400000000>; +}; + &dsi { panel@0 { compatible = "samsung,s6e3ha2"; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts index 2fbf3a860316..7891a31adc17 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts @@ -18,6 +18,40 @@ compatible = "samsung,tm2e", "samsung,exynos5433"; }; +&cmu_disp { + /* + * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned + * clocks properties for DISP CMU for each board to keep them together + * for easier review and maintenance. + */ + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, + <&cmu_disp CLK_MOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; + assigned-clock-parents = <0>, <0>, + <&cmu_mif CLK_ACLK_DISP_333>, + <&cmu_mif CLK_SCLK_DSIM0_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, + <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; + assigned-clock-rates = <278000000>, <400000000>; +}; + &ldo31_reg { regulator-name = "TSP_VDD_1.8V_AP"; regulator-min-microvolt = <1800000>;