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Mon, 30 Jan 2017 10:57:46 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20170130105746eucas1p1232fb56b92e5939beb7ee65670422860~eh3WVUttL1086810868eucas1p1f; Mon, 30 Jan 2017 10:57:46 +0000 (GMT) X-AuditID: cbfec7f5-f79d06d000004445-89-588f1c2a8ebd Received: from eusync4.samsung.com ( [203.254.199.214]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 69.38.06687.D6C1F885; Mon, 30 Jan 2017 10:58:53 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OKL001FKAG62W70@eusync4.samsung.com>; Mon, 30 Jan 2017 10:57:46 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi , Andrzej Hajda Subject: [PATCH v3 3/3 REBASED] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e Date: Mon, 30 Jan 2017 11:57:36 +0100 Message-id: <1485773856-22707-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <20170128152846.ychltfggmlrgrwwx@kozik-lap> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrPIsWRmVeSWpSXmKPExsWy7djP87paMv0RBtf2KVvcWneO1WLjjPWs Fte/PGe1OH9+A7vFjPP7mCzWHrnLbnH4TTurA7vHplWdbB59W1YxenzeJBfAHMVlk5Kak1mW WqRvl8CV0bleuWCqbsW1M11sDYw/VbsYOTkkBEwkju1qZYSwxSQu3FvP1sXIxSEksJRRYtX/ DnYI5zOjxM33V9nhOlqbmCESyxglZi75xwThNDBJrDq/hwmkik3AUKLrbRcbiC0ioCrxuW0B 2ChmgS4mif1XGllAEsICORLzZ58BK2IBKrq0vQnsEF4BD4mlH9ewQKyTkzh5bDIriM0pYAF0 7CEWkEESAo/ZJJYuPwu0jQPIkZXYdIAZot5FYubxBiYIW1ji1fEtUGfLSHR2HISK9zNKNLVq Q9gzGCXOveWFsK0lDh+/CLaLWYBPYtK26cwQ43klOtqEIEo8JHbf/Qo1xlFi7s/trBDPdzNK dDQsZpnAKLOAkWEVo0hqaXFuemqxqV5xYm5xaV66XnJ+7iZGYLSe/nf86w7GpcesDjEKcDAq 8fDeEO6LEGJNLCuuzD3EKMHBrCTC+0eoP0KINyWxsiq1KD++qDQntfgQozQHi5I4754FV8KF BNITS1KzU1MLUotgskwcnFINjFc/1ulJl975Jae0o08xcItQfrhM3aTdp4/Fv2zJOz+j4dKl WR+33C1asqzYMW9ngp+x4OIXfCr5titMrbecyP5RrS6bHJJTzMG329R7QeTxN0URLLud+a1i Ntad5tj3Ye2F35zn1uZNLlzTeD45ry3b+P9vwSdXfq7xL3p+4jvbtd1qx9fe3KnEUpyRaKjF XFScCACPb4qF0gIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLLMWRmVeSWpSXmKPExsVy+t/xa7q5Mv0RBmueiVncWneO1WLjjPWs Fte/PGe1OH9+A7vFjPP7mCzWHrnLbnH4TTurA7vHplWdbB59W1YxenzeJBfAHOVmk5GamJJa pJCal5yfkpmXbqsUGuKma6GkkJeYm2qrFKHrGxKkpFCWmFMK5BkZoAEH5wD3YCV9uwS3jM71 ygVTdSuunelia2D8qdrFyMkhIWAicay1iRnCFpO4cG89WxcjF4eQwBJGiVmbfjJBOE1MEss3 9bOBVLEJGEp0ve0Cs0UEVCU+ty1gB7GZBXqYJLq6BUBsYYEciSWnv4HVsADVXNrexAhi8wp4 SCz9uIYFYpucxMljk1lBbE4BC4ljuw4BxTmAlplL7Oxkn8DIu4CRYRWjSGppcW56brGhXnFi bnFpXrpecn7uJkZg0G479nPzDsZLG4MPMQpwMCrx8N4Q7osQYk0sK67MPcQowcGsJML7R6g/ Qog3JbGyKrUoP76oNCe1+BCjKdBNE5mlRJPzgRGVVxJvaGJobmloZGxhYW5kpCTOW/LhSriQ QHpiSWp2ampBahFMHxMHp1QDYwHX3JOqGY7OXxUXX35sUHinQ/nB/Ak9q39e8ojc8mIKx69V VQazZmwOXLnRcr74/bVhvLvOx09rO6K80DP98v4tsp8OFMle3ynO8jLysLzmPbGjM80+nFg8 45u99ZmLC7i2HVk9cTu7x0q2/bfc9V9+cws9m/VSpf74xaYGT+4rs9KbXjfxpxxQYinOSDTU Yi4qTgQASJopJXACAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170130105746eucas1p1232fb56b92e5939beb7ee65670422860 X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170130105746eucas1p1232fb56b92e5939beb7ee65670422860 X-RootMTR: 20170130105746eucas1p1232fb56b92e5939beb7ee65670422860 References: <20170128152846.ychltfggmlrgrwwx@kozik-lap> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add initial clock configuration for display subsystem for Exynos5433 based TM2/TM2e boards in device tree in order to avoid dependency on the configuration left by the bootloader. This initial configuration is also needed to ensure that display subsystem is operational if display power domain gets turned off before clock controller is probed and the inital clock configuration left by the bootloader saved. TM2 and TM2e uses different rate for DISP PLL clock, but for better maintainability all 'assigned-clocks-*' properties for DISP CMU are defines in each board dts instead of redefining the rates property. Signed-off-by: Marek Szyprowski Reviewed-by: Chanwoo Choi --- Changelog: v3 resend: - rebased onto Linux next-20170130 v3: - added comment about DISP CMU clocks configuration on TM2 and TM2e --- .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 -------- arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 34 ++++++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 34 ++++++++++++++++++++++ 3 files changed, 68 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 53fd0683d400..098ad557fee3 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -217,18 +217,6 @@ assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>; }; -&cmu_disp { - assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, - <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; - assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, - <0>, - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; - assigned-clock-rates = <0>, <400000000>; -}; - &cmu_fsys { assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, <&cmu_top CLK_MOUT_SCLK_USBHOST30>, diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts index ddba2f889326..dea0a6f5bc18 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts @@ -18,6 +18,40 @@ compatible = "samsung,tm2", "samsung,exynos5433"; }; +&cmu_disp { + /* + * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned + * clocks properties for DISP CMU for each board to keep them together + * for easier review and maintenance. + */ + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, + <&cmu_disp CLK_MOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; + assigned-clock-parents = <0>, <0>, + <&cmu_mif CLK_ACLK_DISP_333>, + <&cmu_mif CLK_SCLK_DSIM0_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, + <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; + assigned-clock-rates = <250000000>, <400000000>; +}; + &hsi2c_9 { status = "okay"; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts index 2fbf3a860316..7891a31adc17 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts @@ -18,6 +18,40 @@ compatible = "samsung,tm2e", "samsung,exynos5433"; }; +&cmu_disp { + /* + * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned + * clocks properties for DISP CMU for each board to keep them together + * for easier review and maintenance. + */ + assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, + <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, + <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, + <&cmu_disp CLK_MOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; + assigned-clock-parents = <0>, <0>, + <&cmu_mif CLK_ACLK_DISP_333>, + <&cmu_mif CLK_SCLK_DSIM0_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, + <&cmu_disp CLK_FOUT_DISP_PLL>, + <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; + assigned-clock-rates = <278000000>, <400000000>; +}; + &ldo31_reg { regulator-name = "TSP_VDD_1.8V_AP"; regulator-min-microvolt = <1800000>;