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Mon, 30 Jan 2017 12:38:40 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20170130123839eucas1p2bbbf9dd2c3d9cc1dbff1830a1e7e22cb~ejPcTqnj32037920379eucas1p2P; Mon, 30 Jan 2017 12:38:39 +0000 (GMT) X-AuditID: cbfec7f1-f793f6d000007796-47-588f33d04d58 Received: from eusync3.samsung.com ( [203.254.199.213]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id B2.D6.06687.2143F885; Mon, 30 Jan 2017 12:39:46 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OKL0038AF49F510@eusync3.samsung.com>; Mon, 30 Jan 2017 12:38:39 +0000 (GMT) From: Marek Szyprowski To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , Lee Jones , Bartlomiej Zolnierkiewicz Subject: [PATCH v3 5/7] mfd: exynos-lpass: Add support for clocks Date: Mon, 30 Jan 2017 13:38:26 +0100 Message-id: <1485779908-32147-6-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1485779908-32147-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLIsWRmVeSWpSXmKPExsWy7djPc7oXjPsjDO5cErHYOGM9q8X58xvY Le5/PcpoMeXPciaLTY+vsVpsnv+H0eLyrjlsFjPO72OyWHvkLrvF4TftrBardv1hdOD22Dnr LrvHplWdbB53ru1h89i8pN6jb8sqRo/Pm+QC2KK4bFJSczLLUov07RK4Mt59zC9okq3Y3TOD tYHxq3gXIyeHhICJxNQNC5kgbDGJC/fWs4HYQgJLGSXO38uFsD8zSpxeJQZT/2rDbKB6LqD4 MkaJW0uOs0M4DUwSVztfMYNUsQkYSnS97WIDSYgItDNK3O3rAGthFtjEJNG25ARYlbCAo8Tb WxtZQGwWAVWJxmn/we7gFfCQuHZiJzPEPjmJk8cms4LYnAKeElueHoKKT2aX6P5b38XIAWTL Smw6wAxhukh86I2FqBCWeHV8CzuELSPR2XEQ6st+RommVm0IewajxLm3vBC2tcTh4xfBNjEL 8ElM2jYdaiSvREebEITpIbHwnAVEtaPEuvdvWCFen8Mo8ervY+YJjDILGBlWMYqklhbnpqcW G+kVJ+YWl+al6yXn525iBEb66X/HP+5gfH/C6hCjAAejEg/vDeG+CCHWxLLiytxDjBIczEoi vCdV+yOEeFMSK6tSi/Lji0pzUosPMUpzsCiJ8+5ZcCVcSCA9sSQ1OzW1ILUIJsvEwSnVwJg/ iT0q8tjzc28ainW2d9zqW9PRzKWx+mP508nX5bNVpOrVC/2q3gZndPfxJTP3udxdsHpH5b2n Kp1+fflv7ky2zfnYtP53b1uq2oU5VfMdZs3PXTjhToDI8bNcvnI+p24v8VIQMPh4Jf+9XNLe fLG2eYV+rUUsSR5LfjP9XZRhpHFQ2UJxphJLcUaioRZzUXEiAG5JFL3wAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpikeLIzCtJLcpLzFFi42I5/e/4VV0hk/4Ig9f7LCw2zljPanH+/AZ2 i/tfjzJaTPmznMli0+NrrBab5/9htLi8aw6bxYzz+5gs1h65y25x+E07q8WqXX8YHbg9ds66 y+6xaVUnm8eda3vYPDYvqffo27KK0ePzJrkAtig3m4zUxJTUIoXUvOT8lMy8dFul0BA3XQsl hbzE3FRbpQhd35AgJYWyxJxSIM/IAA04OAe4Byvp2yW4Zbz7mF/QJFuxu2cGawPjV/EuRk4O CQETiVcbZjNB2GISF+6tZ+ti5OIQEljCKHHi/AMop4lJouv2OjaQKjYBQ4mut11gCRGBdkaJ 17evMYE4zAJbgKo2XWQHqRIWcJR4e2sjC4jNIqAq0TjtP9gOXgEPiWsndjJD7JOTOHlsMiuI zSngKbHl6SGwuBBQzfkb/1kmMPIuYGRYxSiSWlqcm55bbKhXnJhbXJqXrpecn7uJERj+2479 3LyD8dLG4EOMAhyMSjy8N4T7IoRYE8uKK3MPMUpwMCuJ8J5U7Y8Q4k1JrKxKLcqPLyrNSS0+ xGgKdNREZinR5HxgbOaVxBuaGJpbGhoZW1iYGxkpifOWfLgSLiSQnliSmp2aWpBaBNPHxMEp 1cDoYa/Dmxvt+evDxYyS6ikyjjZeYTN2ZYmfCFX3D36zu9zdzKx+n8n3rLSfj5YlXn/9cfN2 1SlbHB7eWSE8J3jHRve9/DyurYLhu3702Ad7Fdt9a/LQ33oi0/MLk+Y6pRuXqhN5HnyOCXE1 f/hgo/WhHxHaVfcPVfMbeD1hq+q4739vWsbf02+VWIozEg21mIuKEwE9jkaWlQIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170130123839eucas1p2bbbf9dd2c3d9cc1dbff1830a1e7e22cb X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170130123839eucas1p2bbbf9dd2c3d9cc1dbff1830a1e7e22cb X-RootMTR: 20170130123839eucas1p2bbbf9dd2c3d9cc1dbff1830a1e7e22cb References: <1485779908-32147-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Exynos LPASS requires some clocks to be enabled to make any access to its registers. This patch adds code for handling such clocks. For current set of registers it is enough to keep sfr0_ctrl clock enabled. Till now it worked only because those clocks were enabled by bootloader and driver probe() happened before they were disabled by clock core because of lack of users. Handling those clocks is also needed to make it possible to enable support for audio power domain. This patch requires adding sfr0_ctrl clock to device tree. Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski Acked-by: Sylwester Nawrocki --- .../devicetree/bindings/mfd/samsung,exynos5433-lpass.txt | 6 ++++++ drivers/mfd/exynos-lpass.c | 10 ++++++++++ 2 files changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt index a8deaee82c44..df664018c148 100644 --- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt +++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.txt @@ -5,6 +5,10 @@ Required properties: - compatible : "samsung,exynos5433-lpass" - reg : should contain the LPASS top SFR region location and size + - clock-names : should contain following required clocks: "sfr0_ctrl" + - clocks : should contain clock specifiers of all clocks, which + input names have been specified in clock-names + property, in same order. - #address-cells : should be 1 - #size-cells : should be 1 - ranges : must be present @@ -24,6 +28,8 @@ Example: audio-subsystem { compatible = "samsung,exynos5433-lpass"; reg = <0x11400000 0x100>, <0x11500000 0x08>; + clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>; + clock-names = "sfr0_ctrl"; #address-cells = <1>; #size-cells = <1>; ranges; diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c index 17915daa2e80..be264988bdc9 100644 --- a/drivers/mfd/exynos-lpass.c +++ b/drivers/mfd/exynos-lpass.c @@ -14,6 +14,7 @@ * only version 2 as published by the Free Software Foundation. */ +#include #include #include #include @@ -52,6 +53,7 @@ struct exynos_lpass { /* pointer to the LPASS TOP regmap */ struct regmap *top; + struct clk *sfr0_clk; }; static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask) @@ -71,6 +73,8 @@ static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask) static void exynos_lpass_enable(struct exynos_lpass *lpass) { + clk_prepare_enable(lpass->sfr0_clk); + /* Unmask SFR, DMA and I2S interrupt */ regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S); @@ -88,6 +92,8 @@ static void exynos_lpass_disable(struct exynos_lpass *lpass) /* Mask any unmasked IP interrupt sources */ regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0); regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0); + + clk_disable_unprepare(lpass->sfr0_clk); } static const struct regmap_config exynos_lpass_reg_conf = { @@ -114,6 +120,10 @@ static int exynos_lpass_probe(struct platform_device *pdev) if (IS_ERR(base_top)) return PTR_ERR(base_top); + lpass->sfr0_clk = devm_clk_get(dev, "sfr0_ctrl"); + if (IS_ERR(lpass->sfr0_clk)) + return PTR_ERR(lpass->sfr0_clk); + lpass->top = regmap_init_mmio(dev, base_top, &exynos_lpass_reg_conf); if (IS_ERR(lpass->top)) {