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Mon, 20 Feb 2017 13:39:16 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20170220133915eucas1p205f1ca5970e9e02411b8a1f1fb933244~lAnWT-RzN2257522575eucas1p2_; Mon, 20 Feb 2017 13:39:15 +0000 (GMT) X-AuditID: cbfec7f4-f79716d000006f65-81-58aaf184c29f Received: from eusync1.samsung.com ( [203.254.199.211]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id E9.FA.10233.981FAA85; Mon, 20 Feb 2017 13:39:21 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OLO00HBFDX6PK30@eusync1.samsung.com>; Mon, 20 Feb 2017 13:39:15 +0000 (GMT) From: Marek Szyprowski To: linux-media@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Andrzej Hajda , Krzysztof Kozlowski , Inki Dae , Seung-Woo Kim Subject: [PATCH v2 11/15] media: s5p-mfc: Split variant DMA memory configuration into separate functions Date: Mon, 20 Feb 2017 14:39:00 +0100 Message-id: <1487597944-2000-12-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1487597944-2000-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrEIsWRmVeSWpSXmKPExsWy7djP87otH1dFGCxvELe4te4cq8Wk+xNY LM6f38Bu0bNhK6vFjPP7mCzWHrnLbnH4TTuQO/klmwOHx6ZVnWwefVtWMXp83iQXwBzFZZOS mpNZllqkb5fAlfHu+E/2gp2aFefvX2drYJyh3MXIwSEhYCLxaKlIFyMnkCkmceHeerYuRi4O IYGljBKvpnxnhHA+M0o8ufaVDaLKROLg9LfMEIlljBIvVvZBVTUwSXx6PIEZpIpNwFCi620X WIeIgJPEwll/2UGKmAW+M0p8232aFSQhLJAlMf3FR7AGFgFViX9zjrOA2LwCHhKflsGsk5M4 eWwyK8itnEDxHe3JIHMkBF6zSRy83M0O8YOsxKYDzBCmi8SFgzYQncISr45vYYewZSQuT+5m gbD7GSWaWrUh7BmMEufe8kLY1hKHj18Eu4xZgE9i0rbpUCN5JTrahCBKgA54184KYTtKvH/w Bxpasxklnre9Z5nAKLOAkWEVo0hqaXFuemqxiV5xYm5xaV66XnJ+7iZGYMye/nf8yw7Gxces DjEKcDAq8fBqzFwZIcSaWFZcmXuIUYKDWUmE9/LLVRFCvCmJlVWpRfnxRaU5qcWHGKU5WJTE efcsuBIuJJCeWJKanZpakFoEk2Xi4JRqYGwtt+S+Nblx7ZVlN6ccWC7wyOjL2+vPBDW4ditN P9G1cUPb+x1mK1jP7HHq3fPIaGsWX3/xn82Zi9wLH3AFqhfsus7zrPlhkCDbOt/dF4pTpqQz xP7ML42pXcX235K521FcVvvN/H4vs0XKtmHqAvbT+aPvLOLabZY49fXBQ6dedt48UPJjm7wS S3FGoqEWc1FxIgB2eOeC1QIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMLMWRmVeSWpSXmKPExsVy+t/xy7qdH1dFGDS2ilvcWneO1WLS/Qks FufPb2C36NmwldVixvl9TBZrj9xltzj8ph3InfySzYHDY9OqTjaPvi2rGD0+b5ILYI5ys8lI TUxJLVJIzUvOT8nMS7dVCg1x07VQUshLzE21VYrQ9Q0JUlIoS8wpBfKMDNCAg3OAe7CSvl2C W8a74z/ZC3ZqVpy/f52tgXGGchcjJ4eEgInEwelvmSFsMYkL99azdTFycQgJLGGU2LK1kR3C aWKSWDHrPFgVm4ChRNfbLjYQW0TASWLhrL/sIDazwHdGiWU300BsYYEsiekvPoLVswioSvyb c5wFxOYV8JD4tOwrG8Q2OYmTxyazdjFycHACxXe0J4OEhQTcJb4862WawMi7gJFhFaNIamlx bnpusZFecWJucWleul5yfu4mRmAAbzv2c8sOxq53wYcYBTgYlXh4NWaujBBiTSwrrsw9xCjB wawkwnv55aoIId6UxMqq1KL8+KLSnNTiQ4ymQDdNZJYSTc4HRldeSbyhiaG5paGRsYWFuZGR kjjv1A9XwoUE0hNLUrNTUwtSi2D6mDg4pRoYOZe+CL+yk3nr39ipsYG1xyWlm4sm3TQ6zvOr +0rdpyWpEQ1tLtN3Bvht6P++JulbUPi7lzdiTwSX84rHLt/so/zXba78FY2WMKGVVy5uv8aj dOuX45e3QexZi2YUssgrq4TsmbP66f5FfZ4LGRjNV/+waGTSsL//8MzmyPV7jvXtN6taM6lM QImlOCPRUIu5qDgRAGAMo/J2AgAA X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170220133915eucas1p205f1ca5970e9e02411b8a1f1fb933244 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170220133915eucas1p205f1ca5970e9e02411b8a1f1fb933244 X-RootMTR: 20170220133915eucas1p205f1ca5970e9e02411b8a1f1fb933244 References: <1487597944-2000-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Move code for DMA memory configuration with IOMMU into separate function to make it easier to compare what is being done in each case. Signed-off-by: Marek Szyprowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas --- drivers/media/platform/s5p-mfc/s5p_mfc.c | 102 ++++++++++++++++++------------- 1 file changed, 61 insertions(+), 41 deletions(-) diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c index 4403487a494a..04067bcc3feb 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c @@ -1107,44 +1107,15 @@ static struct device *s5p_mfc_alloc_memdev(struct device *dev, return NULL; } -static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev) +static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev) { struct device *dev = &mfc_dev->plat_dev->dev; void *bank2_virt; dma_addr_t bank2_dma_addr; unsigned long align_size = 1 << MFC_BASE_ALIGN_ORDER; - struct s5p_mfc_priv_buf *fw_buf = &mfc_dev->fw_buf; int ret; /* - * When IOMMU is available, we cannot use the default configuration, - * because of MFC firmware requirements: address space limited to - * 256M and non-zero default start address. - * This is still simplified, not optimal configuration, but for now - * IOMMU core doesn't allow to configure device's IOMMUs channel - * separately. - */ - if (exynos_is_iommu_available(dev)) { - int ret = exynos_configure_iommu(dev, S5P_MFC_IOMMU_DMA_BASE, - S5P_MFC_IOMMU_DMA_SIZE); - if (ret) - return ret; - - mfc_dev->mem_dev[BANK1_CTX] = mfc_dev->mem_dev[BANK2_CTX] = dev; - ret = s5p_mfc_alloc_firmware(mfc_dev); - if (ret) { - exynos_unconfigure_iommu(dev); - return ret; - } - - mfc_dev->dma_base[BANK1_CTX] = fw_buf->dma; - mfc_dev->dma_base[BANK2_CTX] = fw_buf->dma; - vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32)); - - return 0; - } - - /* * Create and initialize virtual devices for accessing * reserved memory regions. */ @@ -1167,7 +1138,7 @@ static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev) return ret; } - mfc_dev->dma_base[BANK1_CTX] = fw_buf->dma; + mfc_dev->dma_base[BANK1_CTX] = mfc_dev->fw_buf.dma; bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK2_CTX], align_size, &bank2_dma_addr, GFP_KERNEL); @@ -1196,22 +1167,71 @@ static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev) return 0; } -static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev) +static void s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev *mfc_dev) { - struct device *dev = &mfc_dev->plat_dev->dev; + device_unregister(mfc_dev->mem_dev[BANK1_CTX]); + device_unregister(mfc_dev->mem_dev[BANK2_CTX]); + vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK1_CTX]); + vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK2_CTX]); +} - s5p_mfc_release_firmware(mfc_dev); +static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev) +{ + struct device *dev = &mfc_dev->plat_dev->dev; + /* + * When IOMMU is available, we cannot use the default configuration, + * because of MFC firmware requirements: address space limited to + * 256M and non-zero default start address. + * This is still simplified, not optimal configuration, but for now + * IOMMU core doesn't allow to configure device's IOMMUs channel + * separately. + */ + int ret = exynos_configure_iommu(dev, S5P_MFC_IOMMU_DMA_BASE, + S5P_MFC_IOMMU_DMA_SIZE); + if (ret) + return ret; - if (exynos_is_iommu_available(dev)) { + mfc_dev->mem_dev[BANK1_CTX] = mfc_dev->mem_dev[BANK2_CTX] = dev; + ret = s5p_mfc_alloc_firmware(mfc_dev); + if (ret) { exynos_unconfigure_iommu(dev); - vb2_dma_contig_clear_max_seg_size(dev); - return; + return ret; } - device_unregister(mfc_dev->mem_dev[BANK1_CTX]); - device_unregister(mfc_dev->mem_dev[BANK2_CTX]); - vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK1_CTX]); - vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK2_CTX]); + mfc_dev->dma_base[BANK1_CTX] = mfc_dev->fw_buf.dma; + mfc_dev->dma_base[BANK2_CTX] = mfc_dev->fw_buf.dma; + vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32)); + + return 0; +} + +static void s5p_mfc_unconfigure_common_memory(struct s5p_mfc_dev *mfc_dev) +{ + struct device *dev = &mfc_dev->plat_dev->dev; + + exynos_unconfigure_iommu(dev); + vb2_dma_contig_clear_max_seg_size(dev); +} + +static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev) +{ + struct device *dev = &mfc_dev->plat_dev->dev; + + if (exynos_is_iommu_available(dev)) + return s5p_mfc_configure_common_memory(mfc_dev); + else + return s5p_mfc_configure_2port_memory(mfc_dev); +} + +static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev) +{ + struct device *dev = &mfc_dev->plat_dev->dev; + + s5p_mfc_release_firmware(mfc_dev); + if (exynos_is_iommu_available(dev)) + s5p_mfc_unconfigure_common_memory(mfc_dev); + else + s5p_mfc_unconfigure_2port_memory(mfc_dev); } /* MFC probe function */