From patchwork Fri Feb 24 11:16:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 9589925 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7375B6042B for ; Fri, 24 Feb 2017 11:16:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7A2DC28670 for ; Fri, 24 Feb 2017 11:16:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6EA7328589; Fri, 24 Feb 2017 11:16:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C5D5A28589 for ; Fri, 24 Feb 2017 11:16:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751265AbdBXLQl (ORCPT ); Fri, 24 Feb 2017 06:16:41 -0500 Received: from mailout3.w1.samsung.com ([210.118.77.13]:13096 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751115AbdBXLQj (ORCPT ); Fri, 24 Feb 2017 06:16:39 -0500 Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0OLV00M9SLZNR880@mailout3.w1.samsung.com>; Fri, 24 Feb 2017 11:16:35 +0000 (GMT) Received: from eusmges3.samsung.com (unknown [203.254.199.242]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20170224111635eucas1p17ff492808917a223244f8cd309a01a29~mNP6pVKdo1623716237eucas1p1U; Fri, 24 Feb 2017 11:16:35 +0000 (GMT) Received: from eucas1p1.samsung.com ( [182.198.249.206]) by eusmges3.samsung.com (EUCPMTA) with SMTP id 41.3D.09557.21610B85; Fri, 24 Feb 2017 11:16:34 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20170224111634eucas1p22340b3b86a835e90ce981a9d9d4dc64a~mNP51DKZZ2933329333eucas1p2f; Fri, 24 Feb 2017 11:16:34 +0000 (GMT) X-AuditID: cbfec7f2-f790f6d000002555-60-58b016123bbd Received: from eusync3.samsung.com ( [203.254.199.213]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id DC.BC.06687.96610B85; Fri, 24 Feb 2017 11:18:01 +0000 (GMT) Received: from AMDC2768.DIGITAL.local ([106.120.43.17]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OLV00G04LZL7Z80@eusync3.samsung.com>; Fri, 24 Feb 2017 11:16:34 +0000 (GMT) From: Andrzej Hajda To: Wolfram Sang , Krzysztof Kozlowski , Javier Martinez Canillas , linux-i2c@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Andrzej Hajda , Bartlomiej Zolnierkiewicz , Marek Szyprowski Subject: [PATCH 1/2] i2c: exynos5: simplify clock frequency handling Date: Fri, 24 Feb 2017 12:16:01 +0100 Message-id: <1487934962-8703-1-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 2.7.4 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMIsWRmVeSWpSXmKPExsWy7djPc7pCYhsiDN4+sbG4te4cq8XGGetZ Ld68XcNkcf78BnaLjr9fGC1mnN/HZLH2yF12i5UnZjE7cHhsWtXJ5rGl/y67R9+WVYweJ089 YfH4vEkugDWKyyYlNSezLLVI3y6BK2PdqadMBX8VK+5tv8nYwHhbuouRk0NCwETiw785jBC2 mMSFe+vZQGwhgaWMEq2Pc7sYuYDsz4wS84//Yu9i5ABr2LIuHSK+jFHi2qaLrBDOf0aJB3d3 M4N0swloSvzdfJMNJCEicIBR4t61dUwgDrNAD6PE3OsNYFXCAi4SN3c0sILYLAKqEi9X3GIB sXkFnCQOPFvEDnGTnMTNc53MIM0SAs/ZJGYt6mKGuENWYtMBZogaF4neTUtYIWxhiVfHt0D1 ykh0dhxkgujtZpT41H+CHcKZwijx78MMqG5ricPHL4J1MwvwSUzaNh1qAa9ER5sQRImHxKY/ DdBAcpRo3dzKCgmkWIm9OxYyT2CUXsDIsIpRJLW0ODc9tdhYrzgxt7g0L10vOT93EyMwak// O/5pB+PXE1aHGAU4GJV4eDterIsQYk0sK67MPcQowcGsJMJbzr4hQog3JbGyKrUoP76oNCe1 +BCjNAeLkjjvngVXwoUE0hNLUrNTUwtSi2CyTBycUg2M+gyCGQeMmraeXrnHrq2oru6v6PwO 9S17r/Quu/d6T9sCW8Nnr9iUzBoOBKxsKnpRU6OwL0Lhvw3TnWlv37XM05l2NDBEuedt49YD F3eb/o/4Zbrw67um0Fna9w6uaJq0s/tW5+t2d16FSN1V7wO+HN7DUHLc1cz60C4liWBN0dYw jhcn7v3XUGIpzkg01GIuKk4EABU9JwXWAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRmVeSWpSXmKPExsVy+t/xq7qZYhsiDB6fEbe4te4cq8XGGetZ Ld68XcNkcf78BnaLjr9fGC1mnN/HZLH2yF12i5UnZjE7cHhsWtXJ5rGl/y67R9+WVYweJ089 YfH4vEkugDXKzSYjNTEltUghNS85PyUzL91WKTTETddCSSEvMTfVVilC1zckSEmhLDGnFMgz MkADDs4B7sFK+nYJbhnrTj1lKvirWHFv+03GBsbb0l2MHBwSAiYSW9aldzFyApliEhfurWfr YuTiEBJYwihxs/UqG0hCSKCRSeJzGyOIzSagKfF3802wIhGBA4wS287+YwdxmAX6GCUa/64C 6xAWcJG4uaOBFcRmEVCVeLniFguIzSvgJHHg2SJ2iHVyEjfPdTJPYORewMiwilEktbQ4Nz23 2FCvODG3uDQvXS85P3cTIzBMtx37uXkH46WNwYcYBTgYlXh4DZ6tixBiTSwrrsw9xCjBwawk wlvOviFCiDclsbIqtSg/vqg0J7X4EKMp0PKJzFKiyfnAGMoriTc0MTS3NDQytrAwNzJSEuct +XAlXEggPbEkNTs1tSC1CKaPiYNTqoGxeNKbR1p7nHw0lkcZm+yZJRUZ3Pd21XSGD3cebo8r PNf1mTd+Xshdzi4Dh3SrhH69lCXW525M+BqYESDxUirrcolSgkpy59dNH8Idbk9edCx9UeWD S9Om7tPXaP2f674yf7KyeRv7N1GNO+bPH+l5PJsR9zbSr9/t9USj6WuYTV3/WRrOlytXYinO SDTUYi4qTgQA5kLfRGkCAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170224111634eucas1p22340b3b86a835e90ce981a9d9d4dc64a X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?UTF-8?B?QW5kcnplaiBIYWpkYRtTUlBPTC1LZXJuZWwgKFRQKRvsgrw=?= =?UTF-8?B?7ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?QW5kcnplaiBIYWpkYRtTUlBPTC1LZXJuZWwgKFRQKRtTYW1z?= =?UTF-8?B?dW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170224111634eucas1p22340b3b86a835e90ce981a9d9d4dc64a X-RootMTR: 20170224111634eucas1p22340b3b86a835e90ce981a9d9d4dc64a References: Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There is no need to keep separate settings for high and fast speed clock. Signed-off-by: Andrzej Hajda Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas --- drivers/i2c/busses/i2c-exynos5.c | 45 +++++++++++----------------------------- 1 file changed, 12 insertions(+), 33 deletions(-) diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c index 04127b8..54df9e6 100644 --- a/drivers/i2c/busses/i2c-exynos5.c +++ b/drivers/i2c/busses/i2c-exynos5.c @@ -168,8 +168,6 @@ */ #define HSI2C_HS_TX_CLOCK 1000000 #define HSI2C_FS_TX_CLOCK 100000 -#define HSI2C_HIGH_SPD 1 -#define HSI2C_FAST_SPD 0 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000)) @@ -200,15 +198,7 @@ struct exynos5_i2c { int trans_done; /* Controller operating frequency */ - unsigned int fs_clock; - unsigned int hs_clock; - - /* - * HSI2C Controller can operate in - * 1. High speed upto 3.4Mbps - * 2. Fast speed upto 1Mbps - */ - int speed_mode; + unsigned int op_clock; /* Version of HS-I2C Hardware */ struct exynos_hsi2c_variant *variant; @@ -279,7 +269,7 @@ static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c) * Returns 0 on success, -EINVAL if the cycle length cannot * be calculated. */ -static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode) +static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings) { u32 i2c_timing_s1; u32 i2c_timing_s2; @@ -292,8 +282,9 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode) unsigned int t_sr_release; unsigned int t_ftl_cycle; unsigned int clkin = clk_get_rate(i2c->clk); - unsigned int op_clk = (mode == HSI2C_HIGH_SPD) ? - i2c->hs_clock : i2c->fs_clock; + unsigned int op_clk = hs_timings ? i2c->op_clock : + (i2c->op_clock >= HSI2C_HS_TX_CLOCK) ? HSI2C_FS_TX_CLOCK : + i2c->op_clock; int div, clk_cycle, temp; /* @@ -344,7 +335,7 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode) div, t_sr_release); dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd); - if (mode == HSI2C_HIGH_SPD) { + if (hs_timings) { writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1); writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2); writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); @@ -364,14 +355,14 @@ static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c) * Configure the Fast speed timing values * Even the High Speed mode initially starts with Fast mode */ - if (exynos5_i2c_set_timing(i2c, HSI2C_FAST_SPD)) { + if (exynos5_i2c_set_timing(i2c, false)) { dev_err(i2c->dev, "HSI2C FS Clock set up failed\n"); return -EINVAL; } /* configure the High speed timing values */ - if (i2c->speed_mode == HSI2C_HIGH_SPD) { - if (exynos5_i2c_set_timing(i2c, HSI2C_HIGH_SPD)) { + if (i2c->op_clock >= HSI2C_HS_TX_CLOCK) { + if (exynos5_i2c_set_timing(i2c, true)) { dev_err(i2c->dev, "HSI2C HS Clock set up failed\n"); return -EINVAL; } @@ -397,7 +388,7 @@ static void exynos5_i2c_init(struct exynos5_i2c *i2c) i2c->regs + HSI2C_CTL); writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL); - if (i2c->speed_mode == HSI2C_HIGH_SPD) { + if (i2c->op_clock >= HSI2C_HS_TX_CLOCK) { writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)), i2c->regs + HSI2C_ADDR); i2c_conf |= HSI2C_HS_MODE; @@ -734,26 +725,14 @@ static int exynos5_i2c_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct exynos5_i2c *i2c; struct resource *mem; - unsigned int op_clock; int ret; i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL); if (!i2c) return -ENOMEM; - if (of_property_read_u32(np, "clock-frequency", &op_clock)) { - i2c->speed_mode = HSI2C_FAST_SPD; - i2c->fs_clock = HSI2C_FS_TX_CLOCK; - } else { - if (op_clock >= HSI2C_HS_TX_CLOCK) { - i2c->speed_mode = HSI2C_HIGH_SPD; - i2c->fs_clock = HSI2C_FS_TX_CLOCK; - i2c->hs_clock = op_clock; - } else { - i2c->speed_mode = HSI2C_FAST_SPD; - i2c->fs_clock = op_clock; - } - } + if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock)) + i2c->op_clock = HSI2C_FS_TX_CLOCK; strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); i2c->adap.owner = THIS_MODULE;