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Mon, 20 Mar 2017 10:56:53 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20170320105653eucas1p27e61ab46b1804c710d4767d94aab27cd~tkdkNEAnE3058230582eucas1p2Z; Mon, 20 Mar 2017 10:56:53 +0000 (GMT) X-AuditID: cbfec7f4-f79716d000006f65-36-58cfb57513b3 Received: from eusync4.samsung.com ( [203.254.199.214]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 93.E7.06687.ED5BFC85; Mon, 20 Mar 2017 10:58:38 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0ON4005OP12KYT20@eusync4.samsung.com>; Mon, 20 Mar 2017 10:56:53 +0000 (GMT) From: Marek Szyprowski To: linux-media@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Andrzej Hajda , Krzysztof Kozlowski , Inki Dae , Seung-Woo Kim Subject: [PATCH v3 11/16] media: s5p-mfc: Split variant DMA memory configuration into separate functions Date: Mon, 20 Mar 2017 11:56:37 +0100 Message-id: <1490007402-30265-12-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1490007402-30265-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKIsWRmVeSWpSXmKPExsWy7djPc7qlW89HGPyeqWVxa905VotJ9yew WJw/v4HdomfDVlaLGef3MVmsPXKX3eLwm3Ygd/JLNgcOj02rOtk8+rasYvT4vEkugDmKyyYl NSezLLVI3y6BK+Pi/XXsBbO1KtYcOcbcwPheuYuRk0NCwETiyfapzBC2mMSFe+vZuhi5OIQE ljJKLL0wBcr5zChx4XgvI0zHrJc3mSASyxgl+q4+hapqYJK4M+sH2Cw2AUOJrrddbCC2iICT xMJZf9lBipgFvjNKfNt9mhUkISyQJXHm51YWEJtFQFVi3tf7YHFeAU+Jm7MWQK2Tkzh5bDJY nBMo/uL6X7BtEgKv2SRmH50M5HAAObISmw5APeEi0fVtBzuELSzx6vgWKFtGorPjIBOE3c8o 0dSqDWHPYJQ495YXwraWOHz8ItguZgE+iUnbpjNDjOeV6GgTgijxkGg5NRVqpKNEw4cLLBDP z2GU2Pn6M+MERpkFjAyrGEVSS4tz01OLTfSKE3OLS/PS9ZLzczcxAiP39L/jX3YwLj5mdYhR gINRiYf3xqVzEUKsiWXFlbmHGCU4mJVEeD/OPR8hxJuSWFmVWpQfX1Sak1p8iFGag0VJnHfP givhQgLpiSWp2ampBalFMFkmDk6pBkariMKd2yMSHKo1V1Y2cXzellGwP8BPdm6iy4KVMz49 rHv2f8vy+RVxfvxHwnf/t7924XNFuG/23qZ3q4x1OqeXhc1s13IMXJ/zNPHvzKI77pM4LNIF CvbM2lv4UKfxoTO/molE1N3WoqgD3h0nOzW8D689yux24RiTcaXkrWeuO/OybI4sZ1JiKc5I NNRiLipOBAAX+HNr2AIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCLMWRmVeSWpSXmKPExsVy+t/xa7r3tp6PMFjxxsbi1rpzrBaT7k9g sTh/fgO7Rc+GrawWM87vY7JYe+Quu8XhN+1A7uSXbA4cHptWdbJ59G1ZxejxeZNcAHOUm01G amJKapFCal5yfkpmXrqtUmiIm66FkkJeYm6qrVKErm9IkJJCWWJOKZBnZIAGHJwD3IOV9O0S 3DIu3l/HXjBbq2LNkWPMDYzvlbsYOTkkBEwkZr28yQRhi0lcuLeerYuRi0NIYAmjxNbLc1gh nCYmiaMre9lAqtgEDCW63naB2SICThILZ/1lB7GZBb4zSiy7mQZiCwtkSZz5uZUFxGYRUJWY 9/U+K4jNK+ApcXPWAkaIbXISJ49NBotzAsVfXP8LNlNIwENi3eeJTBMYeRcwMqxiFEktLc5N zy021CtOzC0uzUvXS87P3cQIDOFtx35u3sF4aWPwIUYBDkYlHl6Dq+cihFgTy4orcw8xSnAw K4nwfpx7PkKINyWxsiq1KD++qDQntfgQoynQUROZpUST84HxlVcSb2hiaG5paGRsYWFuZKQk zlvy4Uq4kEB6YklqdmpqQWoRTB8TB6dUA2N1+0LtB5MYZpk8v1Xtqbviw49lMz+yMKf8MT9b tVKt4dqKFWsu3HqQsXLRVzN9vVvZVl4X0w/t4Wm+wrF3jtRUw8vvIt7GTz/1V2f6VKst883q HyrMv5t6vWcKnw9DiNaFlo+zGNdqPfjIe2vqtKhaK/E7tv7big5/OM6r1ZgdNKn5qc/v0/vn KLEUZyQaajEXFScCAGbjmtp3AgAA X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170320105653eucas1p27e61ab46b1804c710d4767d94aab27cd X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170320105653eucas1p27e61ab46b1804c710d4767d94aab27cd X-RootMTR: 20170320105653eucas1p27e61ab46b1804c710d4767d94aab27cd References: <1490007402-30265-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Move code for DMA memory configuration with IOMMU into separate function to make it easier to compare what is being done in each case. Signed-off-by: Marek Szyprowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Acked-by: Andrzej Hajda Tested-by: Smitha T Murthy --- drivers/media/platform/s5p-mfc/s5p_mfc.c | 102 ++++++++++++++++++------------- 1 file changed, 61 insertions(+), 41 deletions(-) diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c index 16f4ba4f25ee..ff3bb8af2423 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c @@ -1102,44 +1102,15 @@ static struct device *s5p_mfc_alloc_memdev(struct device *dev, return NULL; } -static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev) +static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev) { struct device *dev = &mfc_dev->plat_dev->dev; void *bank2_virt; dma_addr_t bank2_dma_addr; unsigned long align_size = 1 << MFC_BASE_ALIGN_ORDER; - struct s5p_mfc_priv_buf *fw_buf = &mfc_dev->fw_buf; int ret; /* - * When IOMMU is available, we cannot use the default configuration, - * because of MFC firmware requirements: address space limited to - * 256M and non-zero default start address. - * This is still simplified, not optimal configuration, but for now - * IOMMU core doesn't allow to configure device's IOMMUs channel - * separately. - */ - if (exynos_is_iommu_available(dev)) { - int ret = exynos_configure_iommu(dev, S5P_MFC_IOMMU_DMA_BASE, - S5P_MFC_IOMMU_DMA_SIZE); - if (ret) - return ret; - - mfc_dev->mem_dev[BANK1_CTX] = mfc_dev->mem_dev[BANK2_CTX] = dev; - ret = s5p_mfc_alloc_firmware(mfc_dev); - if (ret) { - exynos_unconfigure_iommu(dev); - return ret; - } - - mfc_dev->dma_base[BANK1_CTX] = fw_buf->dma; - mfc_dev->dma_base[BANK2_CTX] = fw_buf->dma; - vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32)); - - return 0; - } - - /* * Create and initialize virtual devices for accessing * reserved memory regions. */ @@ -1162,7 +1133,7 @@ static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev) return ret; } - mfc_dev->dma_base[BANK1_CTX] = fw_buf->dma; + mfc_dev->dma_base[BANK1_CTX] = mfc_dev->fw_buf.dma; bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK2_CTX], align_size, &bank2_dma_addr, GFP_KERNEL); @@ -1191,22 +1162,71 @@ static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev) return 0; } -static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev) +static void s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev *mfc_dev) { - struct device *dev = &mfc_dev->plat_dev->dev; + device_unregister(mfc_dev->mem_dev[BANK1_CTX]); + device_unregister(mfc_dev->mem_dev[BANK2_CTX]); + vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK1_CTX]); + vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK2_CTX]); +} - s5p_mfc_release_firmware(mfc_dev); +static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev) +{ + struct device *dev = &mfc_dev->plat_dev->dev; + /* + * When IOMMU is available, we cannot use the default configuration, + * because of MFC firmware requirements: address space limited to + * 256M and non-zero default start address. + * This is still simplified, not optimal configuration, but for now + * IOMMU core doesn't allow to configure device's IOMMUs channel + * separately. + */ + int ret = exynos_configure_iommu(dev, S5P_MFC_IOMMU_DMA_BASE, + S5P_MFC_IOMMU_DMA_SIZE); + if (ret) + return ret; - if (exynos_is_iommu_available(dev)) { + mfc_dev->mem_dev[BANK1_CTX] = mfc_dev->mem_dev[BANK2_CTX] = dev; + ret = s5p_mfc_alloc_firmware(mfc_dev); + if (ret) { exynos_unconfigure_iommu(dev); - vb2_dma_contig_clear_max_seg_size(dev); - return; + return ret; } - device_unregister(mfc_dev->mem_dev[BANK1_CTX]); - device_unregister(mfc_dev->mem_dev[BANK2_CTX]); - vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK1_CTX]); - vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK2_CTX]); + mfc_dev->dma_base[BANK1_CTX] = mfc_dev->fw_buf.dma; + mfc_dev->dma_base[BANK2_CTX] = mfc_dev->fw_buf.dma; + vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32)); + + return 0; +} + +static void s5p_mfc_unconfigure_common_memory(struct s5p_mfc_dev *mfc_dev) +{ + struct device *dev = &mfc_dev->plat_dev->dev; + + exynos_unconfigure_iommu(dev); + vb2_dma_contig_clear_max_seg_size(dev); +} + +static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev) +{ + struct device *dev = &mfc_dev->plat_dev->dev; + + if (exynos_is_iommu_available(dev)) + return s5p_mfc_configure_common_memory(mfc_dev); + else + return s5p_mfc_configure_2port_memory(mfc_dev); +} + +static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev) +{ + struct device *dev = &mfc_dev->plat_dev->dev; + + s5p_mfc_release_firmware(mfc_dev); + if (exynos_is_iommu_available(dev)) + s5p_mfc_unconfigure_common_memory(mfc_dev); + else + s5p_mfc_unconfigure_2port_memory(mfc_dev); } /* MFC probe function */