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Mon, 20 Mar 2017 10:56:52 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20170320105651eucas1p2ff2722b748f1ceb529c4fd844f320c9b~tkdjCh-NM2732027320eucas1p21; Mon, 20 Mar 2017 10:56:51 +0000 (GMT) X-AuditID: cbfec7f5-f79d06d000004445-78-58cfb574feae Received: from eusync4.samsung.com ( [203.254.199.214]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 03.E7.06687.DD5BFC85; Mon, 20 Mar 2017 10:58:37 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0ON4005OP12KYT20@eusync4.samsung.com>; Mon, 20 Mar 2017 10:56:51 +0000 (GMT) From: Marek Szyprowski To: linux-media@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Andrzej Hajda , Krzysztof Kozlowski , Inki Dae , Seung-Woo Kim Subject: [PATCH v3 08/16] media: s5p-mfc: Move firmware allocation to DMA configure function Date: Mon, 20 Mar 2017 11:56:34 +0100 Message-id: <1490007402-30265-9-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1490007402-30265-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMIsWRmVeSWpSXmKPExsWy7djP87olW89HGPTOF7K4te4cq8Wk+xNY LM6f38Bu0bNhK6vFjPP7mCzWHrnLbnH4TTuQO/klmwOHx6ZVnWwefVtWMXp83iQXwBzFZZOS mpNZllqkb5fAldGxX67grFnFobOfmBoYH+t2MXJySAiYSDxp+cIKYYtJXLi3nq2LkYtDSGAp o8T1C2ehnM+MEk/2PmSE6di3+QkzRGIZo8S1U8tZIJwGJokzzZ/AqtgEDCW63naxgdgiAk4S C2f9ZQcpYhb4zijxbfdpsIXCAnESLzdcArNZBFQlvnRNYgGxeQU8JNZ+v8sEsU5O4uSxyWA1 nAKeEi+u/wW7SULgOZvEmr6FQHdwADmyEpsOMEPUu0i8+rAL6iFhiVfHt7BD2DISnR0HoWb2 M0o0tWpD2DMYJc695YWwrSUOH78I1ssswCcxadt0qPG8Eh1tQhAlHhKfe16wQYQdJXZt4YX4 fQ6jxOp9m5gmMMosYGRYxSiSWlqcm55abKpXnJhbXJqXrpecn7uJERi1p/8d/7qDcekxq0OM AhyMSjy8BlfPRQixJpYVV+YeYpTgYFYS4f0493yEEG9KYmVValF+fFFpTmrxIUZpDhYlcd49 C66ECwmkJ5akZqemFqQWwWSZODilGhgXLdnMYK1wxMHHxr21+tTEDxN/ls0+p5DY4567fe66 x/4Llk35Kfy5//C5R7x/+Q+Vn4/YeunTqsVFvO+Eva8FBH5tvRvF0NzraT2lYBPj/v0i9X0P jnIUf35q9Wb7xIDlHzou8O179bhm/9bF9zmSVq2olRSzmOTlFha+TGXKt4NKamsuly8TU2Ip zkg01GIuKk4EAPhmCc3WAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMLMWRmVeSWpSXmKPExsVy+t/xa7p3t56PMGg+rWtxa905VotJ9yew WJw/v4HdomfDVlaLGef3MVmsPXKX3eLwm3Ygd/JLNgcOj02rOtk8+rasYvT4vEkugDnKzSYj NTEltUghNS85PyUzL91WKTTETddCSSEvMTfVVilC1zckSEmhLDGnFMgzMkADDs4B7sFK+nYJ bhkd++UKzppVHDr7iamB8bFuFyMnh4SAicS+zU+YIWwxiQv31rN1MXJxCAksYZQ4MXM6E4TT xCRx8PZPFpAqNgFDia63XWwgtoiAk8TCWX/ZQWxmge+MEstupoHYwgJxEi83XGIFsVkEVCW+ dE0C6+UV8JBY+/0uE8Q2OYmTxyaD1XAKeEq8uP4XbKYQUM26zxOZJjDyLmBkWMUoklpanJue W2yoV5yYW1yal66XnJ+7iREYwNuO/dy8g/HSxuBDjAIcjEo8vAZXz0UIsSaWFVfmHmKU4GBW EuH9OPd8hBBvSmJlVWpRfnxRaU5q8SFGU6CjJjJLiSbnA6MrryTe0MTQ3NLQyNjCwtzISEmc t+TDlXAhgfTEktTs1NSC1CKYPiYOTqkGxjIr9nXH1p2VM21eKLU3LzfkdpnrFOOMYK/79gau pk9jFi7y0/F0VbC/9zAsa6/Gt5/qV3Jkzae6LrFeE/zkUJeV79GKdU41LgaPP9m+zw403iJl 1n9B2OCiTPunMHMjX5kCudsbNhWePy6Su4fbYPuOrxNum/vP6S+7fFm1Td1vsrC/aN0lJZbi jERDLeai4kQANtK3L3YCAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170320105651eucas1p2ff2722b748f1ceb529c4fd844f320c9b X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170320105651eucas1p2ff2722b748f1ceb529c4fd844f320c9b X-RootMTR: 20170320105651eucas1p2ff2722b748f1ceb529c4fd844f320c9b References: <1490007402-30265-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP To complete DMA memory configuration for MFC device, allocation of the firmware buffer is needed, because some parameters are dependant on its base address. Till now, this has been handled in the s5p_mfc_alloc_firmware() function. This patch moves that logic to s5p_mfc_configure_dma_memory() to keep DMA memory related operations in a single place. This way s5p_mfc_alloc_firmware() is simplified and does what it name says. The other consequence of this change is moving s5p_mfc_alloc_firmware() call from the s5p_mfc_probe() function to the s5p_mfc_configure_dma_memory(). Signed-off-by: Marek Szyprowski Reviewed-by: Javier Martinez Canillas Acked-by: Andrzej Hajda Tested-by: Smitha T Murthy --- drivers/media/platform/s5p-mfc/s5p_mfc.c | 62 +++++++++++++++++++++------ drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c | 31 -------------- 2 files changed, 49 insertions(+), 44 deletions(-) diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c index 1fe790d88e70..16f4ba4f25ee 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c @@ -1105,6 +1105,11 @@ static struct device *s5p_mfc_alloc_memdev(struct device *dev, static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev) { struct device *dev = &mfc_dev->plat_dev->dev; + void *bank2_virt; + dma_addr_t bank2_dma_addr; + unsigned long align_size = 1 << MFC_BASE_ALIGN_ORDER; + struct s5p_mfc_priv_buf *fw_buf = &mfc_dev->fw_buf; + int ret; /* * When IOMMU is available, we cannot use the default configuration, @@ -1117,14 +1122,21 @@ static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev) if (exynos_is_iommu_available(dev)) { int ret = exynos_configure_iommu(dev, S5P_MFC_IOMMU_DMA_BASE, S5P_MFC_IOMMU_DMA_SIZE); - if (ret == 0) { - mfc_dev->mem_dev[BANK1_CTX] = - mfc_dev->mem_dev[BANK2_CTX] = dev; - vb2_dma_contig_set_max_seg_size(dev, - DMA_BIT_MASK(32)); + if (ret) + return ret; + + mfc_dev->mem_dev[BANK1_CTX] = mfc_dev->mem_dev[BANK2_CTX] = dev; + ret = s5p_mfc_alloc_firmware(mfc_dev); + if (ret) { + exynos_unconfigure_iommu(dev); + return ret; } - return ret; + mfc_dev->dma_base[BANK1_CTX] = fw_buf->dma; + mfc_dev->dma_base[BANK2_CTX] = fw_buf->dma; + vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32)); + + return 0; } /* @@ -1142,6 +1154,35 @@ static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev) return -ENODEV; } + /* Allocate memory for firmware and initialize both banks addresses */ + ret = s5p_mfc_alloc_firmware(mfc_dev); + if (ret) { + device_unregister(mfc_dev->mem_dev[BANK2_CTX]); + device_unregister(mfc_dev->mem_dev[BANK1_CTX]); + return ret; + } + + mfc_dev->dma_base[BANK1_CTX] = fw_buf->dma; + + bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK2_CTX], align_size, + &bank2_dma_addr, GFP_KERNEL); + if (!bank2_virt) { + mfc_err("Allocating bank2 base failed\n"); + s5p_mfc_release_firmware(mfc_dev); + device_unregister(mfc_dev->mem_dev[BANK2_CTX]); + device_unregister(mfc_dev->mem_dev[BANK1_CTX]); + return -ENOMEM; + } + + /* Valid buffers passed to MFC encoder with LAST_FRAME command + * should not have address of bank2 - MFC will treat it as a null frame. + * To avoid such situation we set bank2 address below the pool address. + */ + mfc_dev->dma_base[BANK2_CTX] = bank2_dma_addr - align_size; + + dma_free_coherent(mfc_dev->mem_dev[BANK2_CTX], align_size, bank2_virt, + bank2_dma_addr); + vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK1_CTX], DMA_BIT_MASK(32)); vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK2_CTX], @@ -1154,6 +1195,8 @@ static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev) { struct device *dev = &mfc_dev->plat_dev->dev; + s5p_mfc_release_firmware(mfc_dev); + if (exynos_is_iommu_available(dev)) { exynos_unconfigure_iommu(dev); vb2_dma_contig_clear_max_seg_size(dev); @@ -1230,10 +1273,6 @@ static int s5p_mfc_probe(struct platform_device *pdev) dev->watchdog_timer.data = (unsigned long)dev; dev->watchdog_timer.function = s5p_mfc_watchdog; - ret = s5p_mfc_alloc_firmware(dev); - if (ret) - goto err_res; - ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); if (ret) goto err_v4l2_dev_reg; @@ -1308,8 +1347,6 @@ static int s5p_mfc_probe(struct platform_device *pdev) err_dec_alloc: v4l2_device_unregister(&dev->v4l2_dev); err_v4l2_dev_reg: - s5p_mfc_release_firmware(dev); -err_res: s5p_mfc_final_pm(dev); err_dma: s5p_mfc_unconfigure_dma_memory(dev); @@ -1351,7 +1388,6 @@ static int s5p_mfc_remove(struct platform_device *pdev) video_device_release(dev->vfd_enc); video_device_release(dev->vfd_dec); v4l2_device_unregister(&dev->v4l2_dev); - s5p_mfc_release_firmware(dev); s5p_mfc_unconfigure_dma_memory(dev); s5p_mfc_final_pm(dev); diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c index 50d698968049..b0cf3970117a 100644 --- a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c @@ -26,9 +26,6 @@ /* Allocate memory for firmware */ int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev) { - void *bank2_virt; - dma_addr_t bank2_dma_addr; - unsigned int align_size = 1 << MFC_BASE_ALIGN_ORDER; struct s5p_mfc_priv_buf *fw_buf = &dev->fw_buf; fw_buf->size = dev->variant->buf_size->fw; @@ -44,35 +41,7 @@ int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev) mfc_err("Allocating bitprocessor buffer failed\n"); return -ENOMEM; } - dev->dma_base[BANK1_CTX] = fw_buf->dma; - - if (HAS_PORTNUM(dev) && IS_TWOPORT(dev)) { - bank2_virt = dma_alloc_coherent(dev->mem_dev[BANK2_CTX], - align_size, &bank2_dma_addr, GFP_KERNEL); - - if (!bank2_virt) { - mfc_err("Allocating bank2 base failed\n"); - dma_free_coherent(dev->mem_dev[BANK1_CTX], fw_buf->size, - fw_buf->virt, fw_buf->dma); - fw_buf->virt = NULL; - return -ENOMEM; - } - - /* Valid buffers passed to MFC encoder with LAST_FRAME command - * should not have address of bank2 - MFC will treat it as a null frame. - * To avoid such situation we set bank2 address below the pool address. - */ - dev->dma_base[BANK2_CTX] = bank2_dma_addr - align_size; - dma_free_coherent(dev->mem_dev[BANK2_CTX], align_size, - bank2_virt, bank2_dma_addr); - - } else { - /* In this case bank2 can point to the same address as bank1. - * Firmware will always occupy the beginning of this area so it is - * impossible having a video frame buffer with zero address. */ - dev->dma_base[BANK2_CTX] = dev->dma_base[BANK1_CTX]; - } return 0; }