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Thu, 30 Mar 2017 13:14:38 +0000 (GMT) X-AuditID: b6c32a37-f79f46d000003503-6b-58dd04bf74b6 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id 54.9B.05715.EB40DD85; Thu, 30 Mar 2017 22:14:38 +0900 (KST) Received: from pankaj.com ([107.108.83.125]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0ONM009R0Q3AAC60@mmp2.samsung.com>; Thu, 30 Mar 2017 22:14:38 +0900 (KST) From: Pankaj Dubey To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: krzk@kernel.org, arnd@arndb.de, m.szyprowski@samsung.com, kgene@kernel.org, m.reichl@fivetechno.de, a.hajda@samsung.com, cwchoi00@gmail.com, javier@osg.samsung.com, Pankaj Dubey Subject: [PATCH v9 09/12] ARM: EXYNOS: introduce exynos_cpu_info struct Date: Thu, 30 Mar 2017 18:47:03 +0530 Message-id: <1490879826-16754-10-git-send-email-pankaj.dubey@samsung.com> X-Mailer: git-send-email 2.7.4 In-reply-to: <1490879826-16754-1-git-send-email-pankaj.dubey@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNIsWRmVeSWpSXmKPExsWy7bCmru5+lrsRBr+/clncWneO1eLvpGPs Fs+Oalu8ebuGyaL/8Wtmi/PnN7BbbHp8jdVixvl9TBYvj/xgtFh75C67xaKtX9gduD1+/5rE 6HHrTr3Hzll32T02repk89i8pN5jSz+Q17dlFaPH501yARxRXDYpqTmZZalF+nYJXBmbDl9m Kug0qGhZ+pW1gfG0ehcjJ4eEgInEvn17WCFsMYkL99azdTFycQgJ7GCUmPf1EiNIQkignUni YLMDTMOW9qtQRXMYJe4u/cEE4bxjlGjavB9sFJuArsST93OZQWwRAW+JyWf+soMUMQtcY5RY 2L0CLCEs4C5xtrMPaBQHB4uAqsTBCyEgYV4BT4lrB54yQmyTk7h5rhOsnBMofvLRNLDNEgKL 2CWePFjPAtIrISArsekAM0S9i8Sv/dNZIGxhiVfHt7BD2NISq/7dYoLo7WaUmDUd5AWQxHpG iQu/kyBse4kDV+aANTML8Em8+9rDCjGfV6KjTQiixEOia/lcJgjbUeLHp2+IkDi0/RvrBEaZ BYwMqxjFUguKc9NTiw0LjPWKE3OLS/PS9ZLzczcxgpOAlvkOxg3nfA4xCnAwKvHwVqy9HSHE mlhWXJl7iFGCg1lJhHch090IId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rxi669FCAmkJ5akZqem FqQWwWSZODilGhilY/d78rPvv3T81TdmqQ1F2xc/MlttaBV/2fcyX0sO+9cHV+7cmvHQ2l+r zuxb51Wdwxxf/8971uwbnJgqI9F9+8ZLphD5XxM3LmkUj14dv/Gn109HnzMHuGeUS/w0Vr5b ul9myw/530Yns/Pa+Np2C7V/jbX95t98TEnIacq5bd6zU5t3KmQqsRRnJBpqMRcVJwIAb9b0 tv4CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupmkeLIzCtJLcpLzFFi42I5/e+xoO4+lrsRBhuXiljcWneO1eLvpGPs Fs+Oalu8ebuGyaL/8Wtmi/PnN7BbbHp8jdVixvl9TBYvj/xgtFh75C67xaKtX9gduD1+/5rE 6HHrTr3Hzll32T02repk89i8pN5jSz+Q17dlFaPH501yARxRbjYZqYkpqUUKqXnJ+SmZeem2 SqEhbroWSgp5ibmptkoRur4hQUoKZYk5pUCekQEacHAOcA9W0rdLcMvYdPgyU0GnQUXL0q+s DYyn1bsYOTkkBEwktrRfZYOwxSQu3FsPZHNxCAnMYpRYv2wiWEJI4B2jxLLXcSA2m4CuxJP3 c5lBbBEBb4nJZ/6yg9jMAlcYJY5OzQSxhQXcJc529gH1cnCwCKhKHLwQAhLmFfCUuHbgKSPE LjmJm+c6wcZwAsVPPpoGtcpDYvnJY4wTGHkXMDKsYpRILUguKE5KzzXMSy3XK07MLS7NS9dL zs/dxAiOiGdSOxgP7nI/xCjAwajEw1ux9naEEGtiWXFl7iFGCQ5mJRHehUx3I4R4UxIrq1KL 8uOLSnNSiw8xmgLdNZFZSjQ5HxiteSXxhibmJubGBhbmlpYmRkrivI2zn4ULCaQnlqRmp6YW pBbB9DFxcEo1MJ7j2ynz+XrTjj/3TeZb/8y9feWo2saDd0/wsHFW3fa9WnHe3E5i94yL327r C7vqrfxaxpX9Wpr5XO0S496NHJbzq6XXcOmKHwhOX7rye72I86Kpr50dD7Zeaam8F3g09dk2 zXl/pql1zGuYxdXZuZbxdPY6cTZ+0V2JtyfuPL+eSS1g0rOWokwlluKMREMt5qLiRADMUyPd ngIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170330131438epcas1p459ce93da17fcd05249eddaef18d5021e X-Msg-Generator: CA X-Sender-IP: 203.254.230.26 X-Local-Sender: =?UTF-8?B?7YyQ7Lm07KaIG1NTSVItVHVybiBLZXkgU29sdXRpb25zGw==?= =?UTF-8?B?7IK87ISx7KCE7J6QGy4vU2VuaW9yIENoaWVmIEVuZ2luZWVy?= X-Global-Sender: =?UTF-8?B?UEFOS0FKIEtVTUFSIERVQkVZG1NTSVItVHVybiBLZXkgU29s?= =?UTF-8?B?dXRpb25zG1NhbXN1bmcgRWxlY3Ryb25pY3MbLi9TZW5pb3IgQ2hpZWYgRW5n?= =?UTF-8?B?aW5lZXI=?= X-Sender-Code: =?UTF-8?B?QzEwG1NXQUhRG0MxMElEMDdJRDAxMDk5Nw==?= CMS-TYPE: 101P X-CMS-RootMailID: 20170330131438epcas1p459ce93da17fcd05249eddaef18d5021e X-RootMTR: 20170330131438epcas1p459ce93da17fcd05249eddaef18d5021e References: <1490879826-16754-1-git-send-email-pankaj.dubey@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Various Exynos SoC has different CPU related information, such as CPU boot register, programming sequence making CPU up/down. Currently this is handled by adding lots of soc_is_exynosMMM checks in the code, in an attempt to remove the dependency of such helper functions specific to each SoC, let's separate this information pertaining to CPU by introducing a new "struct exynos_cpu_info". This struct will contain differences associated with CPU on various Exynos SoC. This can be matched by using generic API "soc_device_match". Signed-off-by: Pankaj Dubey --- arch/arm/mach-exynos/platsmp.c | 146 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 135 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index cb6d199..ff369b9 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -33,6 +34,16 @@ extern void exynos4_secondary_startup(void); +/* + * struct exynos_cpu_info - Exynos CPU related info/operations + * @cpu_boot_reg: computes cpu boot address for requested cpu + */ +struct exynos_cpu_info { + void __iomem* (*cpu_boot_reg)(u32 cpu); +}; + +static const struct exynos_cpu_info *cpu_info; + #ifdef CONFIG_HOTPLUG_CPU static inline void cpu_leave_lowpower(u32 core_id) { @@ -168,27 +179,57 @@ int exynos_cluster_power_state(int cluster) S5P_CORE_LOCAL_PWR_EN); } -static void __iomem *cpu_boot_reg_base(void) +static void __iomem *exynos4210_rev11_cpu_boot_reg(u32 cpu) { - if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1) - return pmu_base_addr + S5P_INFORM5; - return sysram_base_addr; + void __iomem *boot_reg = pmu_base_addr; + + if (!boot_reg) + return IOMEM_ERR_PTR(-ENODEV); + + boot_reg += S5P_INFORM5; + + return boot_reg; } -static inline void __iomem *cpu_boot_reg(int cpu) +static void __iomem *exynos4412_cpu_boot_reg(u32 cpu) { - void __iomem *boot_reg; + void __iomem *boot_reg = sysram_base_addr; - boot_reg = cpu_boot_reg_base(); if (!boot_reg) return IOMEM_ERR_PTR(-ENODEV); - if (soc_is_exynos4412()) - boot_reg += 4*cpu; - else if (soc_is_exynos5420() || soc_is_exynos5800()) - boot_reg += 4; + + boot_reg += 4*cpu; + return boot_reg; } +static void __iomem *exynos5420_cpu_boot_reg(u32 cpu) +{ + void __iomem *boot_reg = sysram_base_addr; + + if (!sysram_base_addr) + return IOMEM_ERR_PTR(-ENODEV); + + boot_reg += 4; + + return boot_reg; +} + +static void __iomem *exynos_common_cpu_boot_reg(u32 cpu) +{ + if (!sysram_base_addr) + return IOMEM_ERR_PTR(-ENODEV); + + return sysram_base_addr; +} + +static inline void __iomem *cpu_boot_reg(int cpu) +{ + if (cpu_info && cpu_info->cpu_boot_reg) + return cpu_info->cpu_boot_reg(cpu); + return NULL; +} + /* * Set wake up by local power mode and execute software reset for given core. * @@ -296,13 +337,84 @@ int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr) return ret; } +static const struct exynos_cpu_info exynos3250_cpu_info = { + .cpu_boot_reg = exynos_common_cpu_boot_reg, +}; + +static const struct exynos_cpu_info exynos5420_cpu_info = { + .cpu_boot_reg = exynos5420_cpu_boot_reg, +}; + +static const struct exynos_cpu_info exynos4210_rev11_cpu_info = { + .cpu_boot_reg = exynos4210_rev11_cpu_boot_reg, +}; + +static const struct exynos_cpu_info exynos4412_cpu_info = { + .cpu_boot_reg = exynos4412_cpu_boot_reg, +}; + +static const struct exynos_cpu_info exynos_common_cpu_info = { + .cpu_boot_reg = exynos_common_cpu_boot_reg, +}; + +static const struct soc_device_attribute exynos_soc_revision[] = { + { + .soc_id = "EXYNOS4210", + .revision = "11", + .data = &exynos4210_rev11_cpu_info + }, { + .soc_id = "EXYNOS4210", + .revision = "10", + .data = &exynos_common_cpu_info + } +}; + +static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { + { + .compatible = "samsung,exynos3250", + .data = &exynos3250_cpu_info + }, { + .compatible = "samsung,exynos4212", + .data = &exynos_common_cpu_info + }, { + .compatible = "samsung,exynos4412", + .data = &exynos4412_cpu_info + }, { + .compatible = "samsung,exynos5250", + .data = &exynos_common_cpu_info + }, { + .compatible = "samsung,exynos5260", + .data = &exynos_common_cpu_info + }, { + .compatible = "samsung,exynos5410", + .data = &exynos_common_cpu_info + }, { + .compatible = "samsung,exynos5420", + .data = &exynos5420_cpu_info + }, { + .compatible = "samsung,exynos5440", + .data = &exynos_common_cpu_info + }, { + .compatible = "samsung,exynos5800", + .data = &exynos5420_cpu_info + }, + { /*sentinel*/ }, +}; + static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; + const struct soc_device_attribute *match; u32 mpidr = cpu_logical_map(cpu); u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); int ret = -ENOSYS; + if (of_machine_is_compatible("samsung,exynos4210")) { + match = soc_device_match(exynos_soc_revision); + if (match) + cpu_info = (const struct exynos_cpu_info *) match->data; + } + /* * Set synchronisation state between this boot processor * and the secondary one @@ -387,6 +499,18 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) { + const struct of_device_id *match; + struct device_node *np; + + if (!of_machine_is_compatible("samsung,exynos4210")) { + np = of_find_matching_node_and_match(NULL, + exynos_pmu_of_device_ids, &match); + if (!np) + pr_err("failed to find supported CPU\n"); + else + cpu_info = (const struct exynos_cpu_info *) match->data; + } + exynos_sysram_init(); exynos_set_delayed_reset_assertion(true);