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Wed, 6 Sep 2017 10:37:31 +0000 (GMT) X-AuditID: cbfec7f1-f793a6d00000326b-e8-59afcfebdc9f Received: from eusync1.samsung.com ( [203.254.199.211]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id B2.A8.18832.BEFCFA95; Wed, 6 Sep 2017 11:37:31 +0100 (BST) Received: from AMDC2768.DIGITAL.local ([106.120.43.17]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OVU00L0NTIFI200@eusync1.samsung.com>; Wed, 06 Sep 2017 11:37:31 +0100 (BST) From: Andrzej Hajda To: Inki Dae Cc: Andrzej Hajda , Bartlomiej Zolnierkiewicz , Marek Szyprowski , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, Tobias Jakobi , Daniel Drake Subject: [PATCH 08/10] drm/exynos/mixer: pass actual mode on MIXER to encoder Date: Wed, 06 Sep 2017 12:36:58 +0200 Message-id: <1504694220-15818-9-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 2.7.4 In-reply-to: <1504694220-15818-1-git-send-email-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMIsWRmVeSWpSXmKPExsWy7djPc7qvz6+PNJjxQc3i1rpzrBYbZ6xn tXg0/zGzxZWv79ksJt2fwGIx4/w+Jou1R+6yW7St/sDqwOGx6HuWx/3u40we/46xe/RtWcXo 8XmTXABrFJdNSmpOZllqkb5dAlfG7jX7WAq+KFe8eb+SpYFxv2wXIweHhICJxL9O9y5GTiBT TOLCvfVsXYxcHEICSxkldp5/xQrhfGaU2Hd4IQtElYnE6wV3WSASyxgljh85zQjh/GeU6Gt/ xg5SxSagKfF38002EFtEQFli1b52dpAiZoFlTBIHbu5iBUkIC/hLdM2dCWazCKhK/Gu5B2bz CjhLLHtyhA1inZzEzXOdzCA2p4CLxKnrn8BukhCYwSbxdvlFqCIXie+zepghbGGJV8e3sEPY MhKdHQeZIBq6GSU+9Z9gh3CmMEr8+zADqsNa4vDxi2CrmQX4JCZtm84MCRpeiY42IYgSD4l/ e1czQtiOEsve97FD/DwdaM6C9YwTGKUXMDKsYhRJLS3OTU8tNtIrTswtLs1L10vOz93ECIza 0/+Of9zB+P6E1SFGAQ5GJR7eE4/XRQqxJpYVV+YeYpTgYFYS4f17bn2kEG9KYmVValF+fFFp TmrxIUZpDhYlcV7bqLZIIYH0xJLU7NTUgtQimCwTB6dUA2OIQuTRNZnmef/kNNZuEJp/MlP7 Hf+yVdM/bbBdbi5ucuVaZ6DJl4+PlnGpXzkiYW+cJH3GS7vVoGSfxezbwi3ZXsrxVpoiLkUJ znyb5l1bx6l92fabyaMXurfN5Fhb121WXHJWXULxb1se8726oPuf+pMld7ru4k1N/uze8bqC 48TrabrqC5VYijMSDbWYi4oTASd5MtvWAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprGLMWRmVeSWpSXmKPExsVy+t/xy7qvz6+PNHgxjdfi1rpzrBYbZ6xn tXg0/zGzxZWv79ksJt2fwGIx4/w+Jou1R+6yW7St/sDqwOGx6HuWx/3u40we/46xe/RtWcXo 8XmTXABrFJdNSmpOZllqkb5dAlfG7jX7WAq+KFe8eb+SpYFxv2wXIyeHhICJxOsFd1kgbDGJ C/fWs3UxcnEICSxhlPj79DczSEJIoJFJ4n5PEojNJqAp8XfzTTYQW0RAWWLVvnZ2kAZmgVVM ErPaesESwgK+Ev+3vwGzWQRUJf613GMFsXkFnCWWPTnCBrFNTuLmuU6wBZwCLhKnrn9ihVjm LDHz4SLGCYy8CxgZVjGKpJYW56bnFhvqFSfmFpfmpesl5+duYgSG1rZjPzfvYLy0MfgQowAH oxIPb8HDdZFCrIllxZW5hxglOJiVRHj/nlsfKcSbklhZlVqUH19UmpNafIhRmoNFSZy3d8/q SCGB9MSS1OzU1ILUIpgsEwenVAPjfI/0O3e2rTx46MNCUbsbyQf3tU7+6LP1at/irHUZekYb +it0mQLduk/6C8xs2eQmc4WlUOSo+/dJ8rJvrVXTzhsomPacKH7y+lrA6zk6EmpxnnM2dmQx zPwRFnJ7wzPeqwnS0Yuas1ReO8cvW/HW1D+dVamAf8P3/TVmrhFpuwW/aonsFTmvxFKckWio xVxUnAgA9R3qbSkCAAA= X-CMS-MailID: 20170906103731eucas1p2a9e4a72215d719fcb0b98096de7bd86f X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?UTF-8?B?QW5kcnplaiBIYWpkYRtTUlBPTC1LZXJuZWwgKFRQKRvsgrw=?= =?UTF-8?B?7ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?QW5kcnplaiBIYWpkYRtTUlBPTC1LZXJuZWwgKFRQKRtTYW1z?= =?UTF-8?B?dW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-CMS-RootMailID: 20170906103731eucas1p2a9e4a72215d719fcb0b98096de7bd86f X-RootMTR: 20170906103731eucas1p2a9e4a72215d719fcb0b98096de7bd86f References: <1504694220-15818-1-git-send-email-a.hajda@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP MIXER in SoCs prior to Exynos5420 supports only 4 video modes: 720x480, 720x576, 1280x720, 1920x1080. Support for other modes can be enabled by manipulating timings of HDMI. To allow it MIXER must pass actual video mode to HDMI, the proper way to do it is to modify adjusted_mode property in crtc::mode_fixup callback. Adding such callback allows also to simplify mixer_cfg_scan code - choosing mode is performed already in crtc::mode_fixup. mode_fixup is also better place to check interlace flag. Signed-off-by: Andrzej Hajda Reviewed-by: Tobias Jakobi --- drivers/gpu/drm/exynos/exynos_mixer.c | 70 +++++++++++++++++++++++++---------- 1 file changed, 50 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index f6ea9d9..5aae82b 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -115,6 +115,7 @@ struct mixer_context { struct clk *sclk_hdmi; struct clk *mout_mixer; enum mixer_version_id mxr_ver; + int scan_value; }; struct mixer_drv_data { @@ -367,23 +368,11 @@ static void mixer_cfg_scan(struct mixer_context *ctx, int width, int height) val = test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? MXR_CFG_SCAN_INTERLACE : MXR_CFG_SCAN_PROGRESSIVE; - /* setup display size */ - if (ctx->mxr_ver == MXR_VER_128_0_0_184) { + if (ctx->mxr_ver == MXR_VER_128_0_0_184) mixer_reg_write(ctx, MXR_RESOLUTION, MXR_MXR_RES_HEIGHT(height) | MXR_MXR_RES_WIDTH(width)); - } else { - /* choosing between proper HD and SD mode */ - if (height <= 480) - val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD; - else if (height <= 576) - val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD; - else if (height <= 720) - val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD; - else if (height <= 1080) - val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD; - else - val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD; - } + else + val |= ctx->scan_value; mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_SCAN_MASK); } @@ -467,11 +456,6 @@ static void mixer_commit(struct mixer_context *ctx) { struct drm_display_mode *mode = &ctx->crtc->base.state->adjusted_mode; - if (mode->flags & DRM_MODE_FLAG_INTERLACE) - __set_bit(MXR_BIT_INTERLACE, &ctx->flags); - else - __clear_bit(MXR_BIT_INTERLACE, &ctx->flags); - mixer_cfg_scan(ctx, mode->hdisplay, mode->vdisplay); mixer_cfg_rgb_fmt(ctx, mode->vdisplay); mixer_run(ctx); @@ -1033,6 +1017,51 @@ static int mixer_mode_valid(struct exynos_drm_crtc *crtc, return MODE_BAD; } +static bool mixer_mode_fixup(struct exynos_drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct mixer_context *ctx = crtc->ctx; + int width = mode->hdisplay, height = mode->vdisplay, i; + + struct { + int hdisplay, vdisplay, htotal, vtotal, scan_val; + } static const modes[] = { + { 720, 480, 858, 525, MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD }, + { 720, 576, 864, 625, MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD }, + { 1280, 720, 1650, 750, MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD }, + { 1920, 1080, 2200, 1125, MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD } + }; + + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + __set_bit(MXR_BIT_INTERLACE, &ctx->flags); + else + __clear_bit(MXR_BIT_INTERLACE, &ctx->flags); + + if (ctx->mxr_ver == MXR_VER_128_0_0_184) + return true; + + for (i = 0; i < ARRAY_SIZE(modes); ++i) + if (width <= modes[i].hdisplay && height <= modes[i].vdisplay) { + ctx->scan_value = modes[i].scan_val; + if (width < modes[i].hdisplay || + height < modes[i].vdisplay) { + adjusted_mode->hdisplay = modes[i].hdisplay; + adjusted_mode->hsync_start = modes[i].hdisplay; + adjusted_mode->hsync_end = modes[i].htotal; + adjusted_mode->htotal = modes[i].htotal; + adjusted_mode->vdisplay = modes[i].vdisplay; + adjusted_mode->vsync_start = modes[i].vdisplay; + adjusted_mode->vsync_end = modes[i].vtotal; + adjusted_mode->vtotal = modes[i].vtotal; + } + + return true; + } + + return false; +} + static const struct exynos_drm_crtc_ops mixer_crtc_ops = { .enable = mixer_enable, .disable = mixer_disable, @@ -1043,6 +1072,7 @@ static const struct exynos_drm_crtc_ops mixer_crtc_ops = { .disable_plane = mixer_disable_plane, .atomic_flush = mixer_atomic_flush, .mode_valid = mixer_mode_valid, + .mode_fixup = mixer_mode_fixup, }; static const struct mixer_drv_data exynos5420_mxr_drv_data = {