From patchwork Tue Oct 24 02:29:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marian Mihailescu X-Patchwork-Id: 10023431 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6D3E560245 for ; Tue, 24 Oct 2017 02:32:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 54AA42876B for ; Tue, 24 Oct 2017 02:32:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4842528957; Tue, 24 Oct 2017 02:32:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 21F682876B for ; Tue, 24 Oct 2017 02:32:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751344AbdJXCc1 (ORCPT ); Mon, 23 Oct 2017 22:32:27 -0400 Received: from mail-pf0-f196.google.com ([209.85.192.196]:54374 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751327AbdJXCc0 (ORCPT ); Mon, 23 Oct 2017 22:32:26 -0400 Received: by mail-pf0-f196.google.com with SMTP id n89so18531935pfk.11; Mon, 23 Oct 2017 19:32:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=dlidRYCJSpOOflghZnRn9ZPdLrb83Ylj4vvNsUcXJvI=; b=gjNpdXlnlQK3dAQx57rwiuNLOR59cty4neYtrYl6nHrVzOAd52t396qGH5PVc8DBhG 2hkYGnPPhGJO/JRVkN7ZcOXz6U9Z8TNVwT6IHIEhOG1ZZxmTh5prJoD2c7mVIWbfM64L HESWKrvBt1p/iZVQkBaYselRLxeT0G3v1ythhKMcZ2cZC208eNWaoWUUYnuOieMSPK++ rLs4Jb72J12turggyiy0CIFLy/TXCQ9gwmuUVGoa1U4I1GeRjuXrRd3DjKfUC+9bagiF job2zWAAEMQfAx4ZT6tH7BQOOpgMLDpp6bCetxfySPEUXjKVodL1T/Q+/WFkYlnJuurJ Ey/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=dlidRYCJSpOOflghZnRn9ZPdLrb83Ylj4vvNsUcXJvI=; b=l/2+4eTegy1ctn18KffoNxuLx0B0ZIQf2FwnDCIj1NQlPNebx0JsEl07t03duJeTJB s9SlGvhms2s1hUmRxVQ4wCVhJZc5VxNvnyUVh1V8AXJ00hnrT2E8Mh/wXN1slMVD/++L TV4Kne/Itq0WzoTJSfzfFR8YvGKU89XOULgou+0PTSU8SwtchXlk8a5wcOQzhm0CBBJA mV7n/AMFLBrUix1t8oya7y4oQhw2kLmbgE9vT2+bij9DnhC8YHkVJt5yuo4V4ps0jli8 eIV4d6Sw23brxL7ouAhYRNJz1MDBz07S8W4urz8bn1crRKVl5VHRDEhzEaU8IpyAW3NE 2mOQ== X-Gm-Message-State: AMCzsaWKu6WxAogXGNJbrE0SHqKuqviuMhp1wh5hH7Luy9MEioFiSWGv s4dnfmE4XC9rvrISpgAmE/k= X-Google-Smtp-Source: ABhQp+TNTegdUyrTfhPuZLo2s7VYW3r29J9JnEFv8iHCQwGvZrbp+iBPAMwDPDkb0nEAJRYo138hIQ== X-Received: by 10.99.108.132 with SMTP id h126mr13260191pgc.434.1508812345597; Mon, 23 Oct 2017 19:32:25 -0700 (PDT) Received: from odroid.telstra.com.au ([58.175.5.73]) by smtp.gmail.com with ESMTPSA id m24sm12880318pgc.76.2017.10.23.19.32.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Oct 2017 19:32:24 -0700 (PDT) From: memeka To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, kgene@kernel.org, krzk@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: memeka , Willy Wolff Subject: [PATCH v2] ARM: dts: exynos: add cpu perf counters to Exynos54xx boards Date: Tue, 24 Oct 2017 12:59:56 +1030 Message-Id: <1508812196-14478-1-git-send-email-mihailescu2m@gmail.com> X-Mailer: git-send-email 2.7.4 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable support for ARM Performance Monitoring Units available in Cortex-A7 and Cortex-A15 CPU cores for Exynos54xx SoCs (5410, 5420 and 5422/5800). The PMUs interrupts are defined in the common exynos54xx.dtsi device tree, but the PMUs are enabled and have their interrupt CPU affinity defined next to each SoC's cpus node. Tested with perf on Odroid XU4 (Exynos5422): armv7_cortex_a7 PMU driver: 5 counters available armv7_cortex_a15 PMU driver: 7 counters available Suggested-by: Marek Szyprowski Signed-off-by: Marian Mihailescu Signed-off-by: Willy Wolff --- Changes since v1: - both Cortex-A7 and Cortex-A15 PMUs are now defined in exynos54xx.dtsi - CPU affinity is defined for each SoC *after* the cpus node entry - PMUs are disabled in exynos54xx.dtsi and enabled for each SoC - cpus labels have been fixed in the interrupt-affinity property for Exynos5410 and Exynos5420 SoCs --- arch/arm/boot/dts/exynos5410.dtsi | 8 ++++++++ arch/arm/boot/dts/exynos5420-cpus.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/exynos5422-cpus.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/exynos54xx.dtsi | 20 ++++++++++++++++++++ 4 files changed, 60 insertions(+) diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 7eab4bc..f42b04b 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -428,4 +428,12 @@ samsung,syscon-phandle = <&pmu_system_controller>; }; +&arm_a15_pmu { + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + status = "okay"; +}; + #include "exynos5410-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi index 5c052d7..518b7d8 100644 --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi @@ -124,3 +124,19 @@ }; }; }; + +&arm_a7_pmu { + interrupt-affinity = <&cpu4>, + <&cpu5>, + <&cpu4>, + <&cpu5>; + status = "okay"; +}; + +&arm_a15_pmu { + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi index ab4c718..92676be 100644 --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -131,3 +131,19 @@ }; }; }; + +&arm_a7_pmu { + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + status = "okay"; +}; + +&arm_a15_pmu { + interrupt-affinity = <&cpu4>, + <&cpu5>, + <&cpu6>, + <&cpu7>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 8ca4fef..f0bd27d 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -79,6 +79,26 @@ interrupts = ; }; + arm_a7_pmu: arm-a7-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + status = "disabled"; + }; + + arm_a15_pmu: arm-a15-pmu { + compatible = "arm,cortex-a15-pmu"; + interrupt-parent = <&combiner>; + interrupts = <1 2>, + <7 0>, + <16 6>, + <19 2>; + status = "disabled"; + }; + sss: sss@10830000 { compatible = "samsung,exynos4210-secss"; reg = <0x10830000 0x300>;