From patchwork Thu Feb 22 12:01:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 10235327 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4659F60224 for ; Thu, 22 Feb 2018 12:04:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 43BF528BEB for ; Thu, 22 Feb 2018 12:04:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 365DE28BED; Thu, 22 Feb 2018 12:04:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CB1CE28BEB for ; Thu, 22 Feb 2018 12:04:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932438AbeBVMES (ORCPT ); Thu, 22 Feb 2018 07:04:18 -0500 Received: from esa1.microchip.iphmx.com ([68.232.147.91]:62285 "EHLO esa1.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932103AbeBVMEM (ORCPT ); Thu, 22 Feb 2018 07:04:12 -0500 X-IronPort-AV: E=Sophos;i="5.47,377,1515481200"; d="scan'208";a="12246010" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 22 Feb 2018 05:04:10 -0700 Received: from m18063-ThinkPad-T460p.microchip.com (10.10.76.4) by chn-sv-exch05.mchp-main.com (10.10.76.106) with Microsoft SMTP Server id 14.3.352.0; Thu, 22 Feb 2018 05:04:10 -0700 From: Claudiu Beznea To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , Claudiu Beznea Subject: [PATCH v3 10/10] pwm: atmel: add push-pull mode support Date: Thu, 22 Feb 2018 14:01:21 +0200 Message-ID: <1519300881-8136-11-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1519300881-8136-1-git-send-email-claudiu.beznea@microchip.com> References: <1519300881-8136-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for PWM push-pull mode. This is only supported by SAMA5D2 SoCs. Signed-off-by: Claudiu Beznea --- drivers/pwm/pwm-atmel.c | 40 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c index d2482fe28cfa..da4b58c1ecf2 100644 --- a/drivers/pwm/pwm-atmel.c +++ b/drivers/pwm/pwm-atmel.c @@ -33,8 +33,11 @@ #define PWM_CMR 0x0 /* Bit field in CMR */ -#define PWM_CMR_CPOL (1 << 9) -#define PWM_CMR_UPD_CDTY (1 << 10) +#define PWM_CMR_CPOL BIT(9) +#define PWM_CMR_UPD_CDTY BIT(10) +#define PWM_CMR_DTHI BIT(17) +#define PWM_CMR_DTLI BIT(18) +#define PWM_CMR_PPM BIT(19) #define PWM_CMR_CPRE_MSK 0xF /* The following registers for PWM v1 */ @@ -219,16 +222,19 @@ static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, { struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); struct pwm_state cstate; + struct pwm_caps caps; unsigned long cprd, cdty; u32 pres, val; int ret; pwm_get_state(pwm, &cstate); + pwm_get_caps(chip, pwm, &caps); if (state->enabled) { if (cstate.enabled && cstate.polarity == state->polarity && - cstate.period == state->period) { + cstate.period == state->period && + cstate.mode == state->mode) { cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, atmel_pwm->data->regs.period); atmel_pwm_calculate_cdty(state, cprd, &cdty); @@ -263,6 +269,18 @@ static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, val &= ~PWM_CMR_CPOL; else val |= PWM_CMR_CPOL; + + /* PWM mode. */ + if (caps.modes & PWM_MODE(PUSH_PULL)) { + if (state->mode == PWM_MODE(PUSH_PULL)) { + val |= PWM_CMR_PPM | PWM_CMR_DTLI; + val &= ~PWM_CMR_DTHI; + } else { + val &= ~(PWM_CMR_PPM | PWM_CMR_DTLI | + PWM_CMR_DTHI); + } + } + atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty); mutex_lock(&atmel_pwm->isr_lock); @@ -315,6 +333,20 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = { }, }; +static const struct atmel_pwm_data atmel_pwm_data_v3 = { + .regs = { + .period = PWMV2_CPRD, + .period_upd = PWMV2_CPRDUPD, + .duty = PWMV2_CDTY, + .duty_upd = PWMV2_CDTYUPD, + }, + .caps = { + .modes = PWM_MODE(NORMAL) | + PWM_MODE(COMPLEMENTARY) | + PWM_MODE(PUSH_PULL), + }, +}; + static const struct platform_device_id atmel_pwm_devtypes[] = { { .name = "at91sam9rl-pwm", @@ -337,7 +369,7 @@ static const struct of_device_id atmel_pwm_dt_ids[] = { .data = &atmel_pwm_data_v2, }, { .compatible = "atmel,sama5d2-pwm", - .data = &atmel_pwm_data_v2, + .data = &atmel_pwm_data_v3, }, { /* sentinel */ },