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Mon, 6 May 2019 15:12:09 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com, Lukasz Luba Subject: [PATCH v7 01/13] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Date: Mon, 6 May 2019 17:11:49 +0200 Message-Id: <1557155521-30949-2-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSWUwTURSGubO002pxKCg3iEuaEBSlCDF4o8RIxGQCiTEmviAGqkwApYAd QKE+FAwIKrsLi0jhAbAIyBq2SCxlCWBBJVFZDNgILojI5kIQKVP07Tvn/P/5T24uhUs7SQcq LCKaVUUowmUCMdHY9cvo2ndyMOBAw5AHqsmtJtHrhSkSFRmMJKr4bgIop7cQQ/23lCjD9AVH AwNPhOh54rQQDWsc0auWBwI0n2YAKHfgKYYqDWNCNJJQLkAd0zdI1D7ki0aWrdFSz3twzJZZ WswmmALNC4Jpzh8TMrW6VAGTdn1GwDybacOY9HodYOr61Mx87c5TIn+xVzAbHhbLqtyOBolD q271CqJabK5mFqULNeCT9U0goiB9ECbqi8mbQExJ6XIA5/pNlmIBwMmCWsAX8wBWzNzFNyxZ 2aUYPygDcDFPi/2ztCQkrfkpSkDLYZPustlgR6vh6Ot23KzB6WkMPv/9kzAPbOkzsHhuHDMz QTvBiQ7DOktoX5he029J2wnfGlPXWUT7wZUU/fpJkH4nhI9WsgTmMEj7wK5WT15vCz931wt5 doSrzUUYzxzUpBUDnq9BU0ahRXMEdnS/WL8Zp/fC6hY3vu0NDaYGwG+3hm++2pjb+BpmN97H +bYEpiRLefUeWH970BK0DZY9vmdZzsCKzB6Cf52HAN6umsUzwa78/2FaAHTAno3hlCEs5x7B XpFzCiUXExEivxCprAVrn6vvT/dcE1h8eV4PaArINks++gwGSElFLBen1ANI4TI7iWLSGCCV BCvi4llVZKAqJpzl9GA7RcjsJWqr8bNSOkQRzV5i2ShWtTHFKJGDBoRoqxz2VfhvcUgebGzb kSuaEZ8r1y0R8aMP1JMlF4e95YEucunE1uWxGvdvdS7aWeeYO6k+ZHFQ8lTnIR/n016r5ZGT pFclUeqnyWlrjQzIqtpfaJUf9KN/2OiqOe6U7jFUgHo9vdNWyIKoD4djk3Lm8zrdL2ef2K3e tGpV0lokI7hQhbsLruIUfwHfezYOWAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrBIsWRmVeSWpSXmKPExsVy+t/xu7qn/C7EGCyYqGmxccZ6VovrX56z Wsw/co7VYvXHx4wWk0/NZbI4051r0f/4NbPF+fMb2C3ONr1ht7jVIGNxedccNovPvUcYLWac 38dksfbIXXaL240r2CwOv2lntdh/xcvi9m8+i28nHjE6CHt8+zqJxWN2w0UWj52z7rJ7bFrV yebR2/yOzePguz1MHn1bVjF6bD5d7fF5k1wAZ5SeTVF+aUmqQkZ+cYmtUrShhZGeoaWFnpGJ pZ6hsXmslZGpkr6dTUpqTmZZapG+XYJexrruU2wFuwQrJszvY29gfMnXxcjJISFgIjFx0jKm LkYuDiGBpYwSFxses0EkxCQm7dvODmELS/y51sUGUfSJUaJnbitQBwcHm4CexI5VhSA1IgL1 Ev1vLoHVMAs0MEus2X6VFSQhLBAssff2TDCbRUBV4uHhI0wgNq+Al0TfxjPMEAvkJG6e6wSz OQW8Jf52HGIEsYWAavZ9/M0ygZFvASPDKkaR1NLi3PTcYiO94sTc4tK8dL3k/NxNjMBY2nbs 55YdjF3vgg8xCnAwKvHwPrC9ECPEmlhWXJl7iFGCg1lJhDfx2bkYId6UxMqq1KL8+KLSnNTi Q4ymQEdNZJYSTc4HxnleSbyhqaG5haWhubG5sZmFkjhvh8DBGCGB9MSS1OzU1ILUIpg+Jg5O qQbGLVv3bKr6w+vb+kK46Yvcxkj/Uq77lfn/+A//DbohMbmp4cruqgN7Hm36o+KssVtGQMxH S7fG/VXnr6O5iqp/Lc6rSzXdquyq23/jnPcO69z2S4/PnfMLEpoT/Nnv4wydpfKaGTN0n5za uMe2TiJ+R/eVV7uPx9TLbJOcO8l9U8w2qytXTCdlKLEUZyQaajEXFScCAKFO+jC7AgAA X-CMS-MailID: 20190506151210eucas1p13c2a4b86a6f987ff34fbe1e2d705fbbf X-Msg-Generator: CA X-RootMTR: 20190506151210eucas1p13c2a4b86a6f987ff34fbe1e2d705fbbf X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190506151210eucas1p13c2a4b86a6f987ff34fbe1e2d705fbbf References: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Define new IDs for clocks used by Dynamic Memory Controller in Exynos5422 SoC. Acked-by: Rob Herring Signed-off-by: Lukasz Luba --- include/dt-bindings/clock/exynos5420.h | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 355f469..bf50d8a 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -60,6 +60,7 @@ #define CLK_MAU_EPLL 159 #define CLK_SCLK_HSIC_12M 160 #define CLK_SCLK_MPHY_IXTAL24 161 +#define CLK_SCLK_BPLL 162 /* gate clocks */ #define CLK_UART0 257 @@ -195,6 +196,16 @@ #define CLK_ACLK432_CAM 518 #define CLK_ACLK_FL1550_CAM 519 #define CLK_ACLK550_CAM 520 +#define CLK_CLKM_PHY0 521 +#define CLK_CLKM_PHY1 522 +#define CLK_ACLK_PPMU_DREX0_0 523 +#define CLK_ACLK_PPMU_DREX0_1 524 +#define CLK_ACLK_PPMU_DREX1_0 525 +#define CLK_ACLK_PPMU_DREX1_1 526 +#define CLK_PCLK_PPMU_DREX0_0 527 +#define CLK_PCLK_PPMU_DREX0_1 528 +#define CLK_PCLK_PPMU_DREX1_0 529 +#define CLK_PCLK_PPMU_DREX1_1 530 /* mux clocks */ #define CLK_MOUT_HDMI 640 @@ -217,6 +228,8 @@ #define CLK_MOUT_EPLL 657 #define CLK_MOUT_MAU_EPLL 658 #define CLK_MOUT_USER_MAU_EPLL 659 +#define CLK_MOUT_SCLK_SPLL 660 +#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 /* divider clocks */ #define CLK_DOUT_PIXEL 768 @@ -243,13 +256,16 @@ #define CLK_DOUT_ACLK300_GSCL 789 #define CLK_DOUT_ACLK400_DISP1 790 #define CLK_DOUT_PCLK_CDREX 791 -#define CLK_DOUT_SCLK_CDREX 792 -#define CLK_DOUT_ACLK_CDREX1 793 -#define CLK_DOUT_CCLK_DREX0 794 -#define CLK_DOUT_CLK2X_PHY0 795 -#define CLK_DOUT_PCLK_CORE_MEM 796 +#define CLK_DOUT_PCLK_DREX0 792 +#define CLK_DOUT_PCLK_DREX1 793 +#define CLK_DOUT_SCLK_CDREX 794 +#define CLK_DOUT_ACLK_CDREX1 795 +#define CLK_DOUT_CCLK_DREX0 796 +#define CLK_DOUT_CLK2X_PHY0 797 +#define CLK_DOUT_PCLK_CORE_MEM 798 +#define CLK_FF_DOUT_SPLL2 799 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 797 +#define CLK_NR_CLKS 800 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */