From patchwork Wed Aug 21 00:33:21 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2847376 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0F7C79F2F4 for ; Wed, 21 Aug 2013 00:33:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1798D2054A for ; Wed, 21 Aug 2013 00:33:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F2C9820529 for ; Wed, 21 Aug 2013 00:33:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751500Ab3HUAd3 (ORCPT ); Tue, 20 Aug 2013 20:33:29 -0400 Received: from mail-bk0-f44.google.com ([209.85.214.44]:46621 "EHLO mail-bk0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751396Ab3HUAd2 (ORCPT ); Tue, 20 Aug 2013 20:33:28 -0400 Received: by mail-bk0-f44.google.com with SMTP id mz10so409525bkb.3 for ; Tue, 20 Aug 2013 17:33:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:user-agent:in-reply-to :references:mime-version:content-transfer-encoding:content-type; bh=CKJtrGQnMJqRAe+I9yVvU9p3xoM6LIfLHqKiU3C1/TM=; b=hcPodf3sN3kdVllU416ujyOnTh2uyq080tN4Nk2yDs/hYtd1meG17hCgGI1OdnFRnw 44APJu5FKw8Ai9SdkYjbICUiK1jahsFU0YWzjr7sxG3piNQ7UbWkniJHcNA9ZhWqZ4m5 4HaYbo3rq/XsEMasaQZ2JV8T+8MrZ+/oryaYaKrJVlz+Fp2xEOTMjBDPpPfI7gYzAaIu gucHdPsg6u7C0VnqbHmrFLaQgvIetW7bC+XByLsXA1g8n6o15lVo86VJagtE85PjKtmf ElmeajPwVhusjgqUKLgryAicKLHIe6EUuxzjmmrn6spM8FQ37W/fidaTUY+zfqvyEw3O tVBg== X-Received: by 10.204.234.5 with SMTP id ka5mr479346bkb.5.1377045207009; Tue, 20 Aug 2013 17:33:27 -0700 (PDT) Received: from flatron.localnet (87-207-52-162.dynamic.chello.pl. [87.207.52.162]) by mx.google.com with ESMTPSA id pk7sm1143885bkb.2.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 20 Aug 2013 17:33:26 -0700 (PDT) From: Tomasz Figa To: Mike Turquette Cc: Kukjin Kim , 'Tomasz Figa' , linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, 'Mark Brown' , 'Arnd Bergmann' , 'Olof Johansson' , stern@rowland.harvard.edu, gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, 'Sylwester Nawrocki' , 'Heiko =?ISO-8859-1?Q?St=FCbner=27?= , 'Thomas Abraham' Subject: [PATCH] clk: samsung: pll: Use new registration method for PLL6552 and PLL6553 Date: Wed, 21 Aug 2013 02:33:21 +0200 Message-ID: <1856348.DCxTucbm8V@flatron> User-Agent: KMail/4.11 (Linux/3.10.6-gentoo; KDE/4.11.0; x86_64; ; ) In-Reply-To: <20130820002258.4443.34197@quantum> References: <1374536965-3545-1-git-send-email-tomasz.figa@gmail.com> <158901ce9b34$c0ac8720$42059560$@org> <20130820002258.4443.34197@quantum> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch modifies PLL6552 and PLL6553 clock drivers to use recently added common Samsung PLL registration method. Signed-off-by: Tomasz Figa --- drivers/clk/samsung/clk-pll.c | 105 +++++------------------------------------- drivers/clk/samsung/clk-pll.h | 6 +-- 2 files changed, 13 insertions(+), 98 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 0775554..7572d1d 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -441,9 +441,6 @@ struct clk * __init samsung_clk_register_pll46xx(const char *name, * PLL6552 Clock Type */ -#define PLL6552_LOCK_REG 0x00 -#define PLL6552_CON_REG 0x0c - #define PLL6552_MDIV_MASK 0x3ff #define PLL6552_PDIV_MASK 0x3f #define PLL6552_SDIV_MASK 0x7 @@ -451,21 +448,14 @@ struct clk * __init samsung_clk_register_pll46xx(const char *name, #define PLL6552_PDIV_SHIFT 8 #define PLL6552_SDIV_SHIFT 0 -struct samsung_clk_pll6552 { - struct clk_hw hw; - void __iomem *reg_base; -}; - -#define to_clk_pll6552(_hw) container_of(_hw, struct samsung_clk_pll6552, hw) - static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct samsung_clk_pll6552 *pll = to_clk_pll6552(hw); + struct samsung_clk_pll *pll = to_clk_pll(hw); u32 mdiv, pdiv, sdiv, pll_con; u64 fvco = parent_rate; - pll_con = __raw_readl(pll->reg_base + PLL6552_CON_REG); + pll_con = __raw_readl(pll->con_reg); mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK; pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK; sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK; @@ -480,48 +470,10 @@ static const struct clk_ops samsung_pll6552_clk_ops = { .recalc_rate = samsung_pll6552_recalc_rate, }; -struct clk * __init samsung_clk_register_pll6552(const char *name, - const char *pname, void __iomem *base) -{ - struct samsung_clk_pll6552 *pll; - struct clk *clk; - struct clk_init_data init; - - pll = kzalloc(sizeof(*pll), GFP_KERNEL); - if (!pll) { - pr_err("%s: could not allocate pll clk %s\n", __func__, name); - return NULL; - } - - init.name = name; - init.ops = &samsung_pll6552_clk_ops; - init.parent_names = &pname; - init.num_parents = 1; - - pll->hw.init = &init; - pll->reg_base = base; - - clk = clk_register(NULL, &pll->hw); - if (IS_ERR(clk)) { - pr_err("%s: failed to register pll clock %s\n", __func__, - name); - kfree(pll); - } - - if (clk_register_clkdev(clk, name, NULL)) - pr_err("%s: failed to register lookup for %s", __func__, name); - - return clk; -} - /* * PLL6553 Clock Type */ -#define PLL6553_LOCK_REG 0x00 -#define PLL6553_CON0_REG 0x0c -#define PLL6553_CON1_REG 0x10 - #define PLL6553_MDIV_MASK 0xff #define PLL6553_PDIV_MASK 0x3f #define PLL6553_SDIV_MASK 0x7 @@ -531,22 +483,15 @@ struct clk * __init samsung_clk_register_pll6552(const char *name, #define PLL6553_SDIV_SHIFT 0 #define PLL6553_KDIV_SHIFT 0 -struct samsung_clk_pll6553 { - struct clk_hw hw; - void __iomem *reg_base; -}; - -#define to_clk_pll6553(_hw) container_of(_hw, struct samsung_clk_pll6553, hw) - static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct samsung_clk_pll6553 *pll = to_clk_pll6553(hw); + struct samsung_clk_pll *pll = to_clk_pll(hw); u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; u64 fvco = parent_rate; - pll_con0 = __raw_readl(pll->reg_base + PLL6553_CON0_REG); - pll_con1 = __raw_readl(pll->reg_base + PLL6553_CON1_REG); + pll_con0 = __raw_readl(pll->con_reg); + pll_con1 = __raw_readl(pll->con_reg + 0x4); mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK; pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK; sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK; @@ -563,40 +508,6 @@ static const struct clk_ops samsung_pll6553_clk_ops = { .recalc_rate = samsung_pll6553_recalc_rate, }; -struct clk * __init samsung_clk_register_pll6553(const char *name, - const char *pname, void __iomem *base) -{ - struct samsung_clk_pll6553 *pll; - struct clk *clk; - struct clk_init_data init; - - pll = kzalloc(sizeof(*pll), GFP_KERNEL); - if (!pll) { - pr_err("%s: could not allocate pll clk %s\n", __func__, name); - return NULL; - } - - init.name = name; - init.ops = &samsung_pll6553_clk_ops; - init.parent_names = &pname; - init.num_parents = 1; - - pll->hw.init = &init; - pll->reg_base = base; - - clk = clk_register(NULL, &pll->hw); - if (IS_ERR(clk)) { - pr_err("%s: failed to register pll clock %s\n", __func__, - name); - kfree(pll); - } - - if (clk_register_clkdev(clk, name, NULL)) - pr_err("%s: failed to register lookup for %s", __func__, name); - - return clk; -} - /* * PLL2550x Clock Type */ @@ -732,6 +643,12 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, else init.ops = &samsung_pll36xx_clk_ops; break; + case pll_6552: + init.ops = &samsung_pll6552_clk_ops; + break; + case pll_6553: + init.ops = &samsung_pll6553_clk_ops; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, pll_clk->name); diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 2f70e88..cd11037 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -17,6 +17,8 @@ enum samsung_pll_type { pll_36xx, pll_2550, pll_2650, + pll_6552, + pll_6553, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \ @@ -64,10 +66,6 @@ extern struct clk * __init samsung_clk_register_pll45xx(const char *name, extern struct clk * __init samsung_clk_register_pll46xx(const char *name, const char *pname, const void __iomem *con_reg, enum pll46xx_type type); -extern struct clk *samsung_clk_register_pll6552(const char *name, - const char *pname, void __iomem *base); -extern struct clk *samsung_clk_register_pll6553(const char *name, - const char *pname, void __iomem *base); extern struct clk * __init samsung_clk_register_pll2550x(const char *name, const char *pname, const void __iomem *reg_base, const unsigned long offset);