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Fri, 9 Jun 2023 19:56:17 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::f7a7:a561:87e9:5fab%6]) with mapi id 15.20.6455.030; Fri, 9 Jun 2023 19:56:17 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Christophe Leroy , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kevin Tian , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Russell King , linuxppc-dev@lists.ozlabs.org, Matthias Brugger , Matthew Rosato , Michael Ellerman , Nicholas Piggin , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Dmitry Osipenko , Marek Szyprowski , Nicolin Chen , Niklas Schnelle , Steven Price , Thierry Reding Subject: [PATCH v3 02/25] iommu: Add IOMMU_DOMAIN_PLATFORM Date: Fri, 9 Jun 2023 16:55:50 -0300 Message-Id: <2-v3-89830a6c7841+43d-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v3-89830a6c7841+43d-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: BY3PR05CA0056.namprd05.prod.outlook.com (2603:10b6:a03:39b::31) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|CY8PR12MB7489:EE_ X-MS-Office365-Filtering-Correlation-Id: 02bec255-ea37-4d12-2c0f-08db692395f0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sGJEtfXI1ndQVOsa8X/gBLiNPJMZ+tllwEhu4ik9cIYZ6zSuw23tTrOGYKjylFRdsnXZjaID53mh964kKi/CwIJZYcddrZymcXEnsbhBescC+cWclvLNm0jaleIymR5yXJn6DNzy933tVae2FS1hj0UfxYa+vjdnIYajpTmQyJGLogIITFb30apRcKl2yEKfOV/EYWVRjfzYlq+td8nQCC+vsa8TDwBpWOuSw+xjoXijYR6qccIQM0+EdCkgzfOlxN6QkekU7pFjWdybYaZek5aNPrvwJ1+Et4gnGHPPv2N4MVIjEisxZ3F+Wx5zhzqFmNaVaPpnsFF01DfsUeJQLPaPjvhPqwjMXqV3pfOAKP+HGgJ6PRp0/CQoFWjQ9IpsHoJtccxrLh1b66J8lbwwjybrMzNVi/Bt3/++3lwSaEmDWWFX7q6yqi79Cx2wxTVTHnL3xAdq94xXHXK3Rz8qwHcM39dtxxMf1DFf12wN+it4y1Jl89d0yeekt1GMAuMX6NY/8yrsyi15KWoc5RdaGtqpkqvbYbaihB714AYsinweQE7HzHHEi3EULI++E+fP7K6lChUU+7917n0FWOI9JJpbL9J0WtEwBBySKWSqhznmEewuPkEZ9UrooYmf07jFeAEkE2VlR4fOcZ65Trj3HJycZsaVYZFcV3s2gVjRGcUSUBTc7P/qfn41tbrFScohCXFIn9TtjD14JfnUMsXLd67k+9nKa0CxIpXg276+Os4ELV2O3lCJJzgQh6tBdY17C4fgZZBJZIsYv2V9kihr1UULdZ/60bx3LbAvBeGfpSA/2+YAa2OY0NMZ01rphuuOfiYBPGK662ircZO+0nxDPTgpe+9//Asx6rB1uPkZrzwirKH+9Nflcqm0ljf4h/yd3PYPAsjKnFemxVEAAcpoCDLJWkSM4k4Ofi8GKqJVSsAgaszHkIjYev9ZhThAXJtQ/wDmZqoMQ5e4gcCAh/SO1UWERg6qGqjH341nRhFWvLZ5h6Z8I7oWzdJu5AjnideYxKJkg8xhPctd55yfo4jt8Hz3lMzaV+UDDhmWP5k9LcBvsdXfIXKqW/jjFhvrB8CuIRB8Ga5MRlAV+L1TU83a2Q8fHTKM3enICFeFq55LTBrKGSLCJ4CioLVa4OfrZSbpQ2t2A+su/Fyx1AbJ5ql5RRw3N5kj1WIaQ33YfiIITFg57Fl1owYRr0SI8m15crHzsGljk3vOwkmZItQSTVqsmVXVTqrOq+VRX6fzL2sF2o4UG7jAm/bGf8kj+Az8DCVNB2+aJgP9cH+eyyJJB2fvELcau1UqOBHSpQxbqyHfILN8Zx6hehoQZZW+SuZDX/PzPdxn42n8u8nEdjyi6jh88tD8euqnF2wtQtHait+7Kbxt8CGTMIO82s6ZNfFpxU8vuN+hVcMrLaOh0gGSXVZ6BPrehih3u5zHLLulPSOqD7JozxarxIb+t1BJPR1ay//+z/WvnknIm5Vrx/LRrpLrjDDEneMIGIXiwGQaiA3K7cCPiOKkSO8uh7a6naKSwXAJ/WB9AMGT3EES2j1HGRqV4mpVx61DUdj/VmylkSJTKUptWMJ7ypF4qccMDgigickt X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 02bec255-ea37-4d12-2c0f-08db692395f0 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2023 19:56:16.5190 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: JhLIz/qZQCynjDd8t4t9FmASXBVuBnYecq6Bfls6etANpNh1b47hYQgcV8B894Xs X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7489 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This is used when the iommu driver is taking control of the dma_ops, currently only on S390 and power spapr. It is designed to preserve the original ops->detach_dev() semantic that these S390 was built around. Provide an opaque domain type and a 'default_domain' ops value that allows the driver to trivially force any single domain as the default domain. Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 14 +++++++++++++- include/linux/iommu.h | 6 ++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index bb840a818525ad..c8f6664767152d 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1644,6 +1644,17 @@ iommu_group_alloc_default_domain(struct iommu_group *group, int req_type) lockdep_assert_held(&group->mutex); + /* + * Allow legacy drivers to specify the domain that will be the default + * domain. This should always be either an IDENTITY or PLATFORM domain. + * Do not use in new drivers. + */ + if (bus->iommu_ops->default_domain) { + if (req_type) + return ERR_PTR(-EINVAL); + return bus->iommu_ops->default_domain; + } + if (req_type) return __iommu_group_alloc_default_domain(bus, group, req_type); @@ -1953,7 +1964,8 @@ void iommu_domain_free(struct iommu_domain *domain) if (domain->type == IOMMU_DOMAIN_SVA) mmdrop(domain->mm); iommu_put_dma_cookie(domain); - domain->ops->free(domain); + if (domain->ops->free) + domain->ops->free(domain); } EXPORT_SYMBOL_GPL(iommu_domain_free); diff --git a/include/linux/iommu.h b/include/linux/iommu.h index c3004eac2f88e8..ef0a0000f09326 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -64,6 +64,7 @@ struct iommu_domain_geometry { #define __IOMMU_DOMAIN_DMA_FQ (1U << 3) /* DMA-API uses flush queue */ #define __IOMMU_DOMAIN_SVA (1U << 4) /* Shared process address space */ +#define __IOMMU_DOMAIN_PLATFORM (1U << 5) #define IOMMU_DOMAIN_ALLOC_FLAGS ~__IOMMU_DOMAIN_DMA_FQ /* @@ -81,6 +82,8 @@ struct iommu_domain_geometry { * invalidation. * IOMMU_DOMAIN_SVA - DMA addresses are shared process addresses * represented by mm_struct's. + * IOMMU_DOMAIN_PLATFORM - Legacy domain for drivers that do their own + * dma_api stuff. Do not use in new drivers. */ #define IOMMU_DOMAIN_BLOCKED (0U) #define IOMMU_DOMAIN_IDENTITY (__IOMMU_DOMAIN_PT) @@ -91,6 +94,7 @@ struct iommu_domain_geometry { __IOMMU_DOMAIN_DMA_API | \ __IOMMU_DOMAIN_DMA_FQ) #define IOMMU_DOMAIN_SVA (__IOMMU_DOMAIN_SVA) +#define IOMMU_DOMAIN_PLATFORM (__IOMMU_DOMAIN_PLATFORM) struct iommu_domain { unsigned type; @@ -256,6 +260,7 @@ struct iommu_iotlb_gather { * @owner: Driver module providing these ops * @identity_domain: An always available, always attachable identity * translation. + * @default_domain: If not NULL this will always be set as the default domain. */ struct iommu_ops { bool (*capable)(struct device *dev, enum iommu_cap); @@ -290,6 +295,7 @@ struct iommu_ops { unsigned long pgsize_bitmap; struct module *owner; struct iommu_domain *identity_domain; + struct iommu_domain *default_domain; }; /**