From patchwork Wed Jun 8 18:31:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Leach X-Patchwork-Id: 9165513 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8A2D3604DB for ; Wed, 8 Jun 2016 18:34:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 80D7E2804C for ; Wed, 8 Jun 2016 18:34:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 75DF02824F; Wed, 8 Jun 2016 18:34:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.9 required=2.0 tests=BAYES_00,FSL_HELO_HOME, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E89FF2804C for ; Wed, 8 Jun 2016 18:34:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161820AbcFHSeW (ORCPT ); Wed, 8 Jun 2016 14:34:22 -0400 Received: from mx0.mattleach.net ([176.58.118.143]:50582 "EHLO mx0.mattleach.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1425067AbcFHScg (ORCPT ); Wed, 8 Jun 2016 14:32:36 -0400 Received: by mx0.mattleach.net (Postfix, from userid 99) id 575046248F; Wed, 8 Jun 2016 19:32:34 +0100 (BST) Received: from victor.home (host109-154-191-76.range109-154.btcentralplus.com [109.154.191.76]) by mx0.mattleach.net (Postfix) with ESMTPSA id 1EA1D62250; Wed, 8 Jun 2016 19:31:25 +0100 (BST) From: Matthew Leach To: Krzysztof Kozlowski , Ben Dooks Cc: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 09/15] ARM: EXYNOS: fixups for big-endian operation Date: Wed, 8 Jun 2016 19:31:04 +0100 Message-Id: <20160608183110.13851-10-matthew@mattleach.net> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160608183110.13851-1-matthew@mattleach.net> References: <20160608183110.13851-1-matthew@mattleach.net> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Dooks If the kernel is built big endian, then using the __raw read and write IO accessors is not going to work as they end up writing big-endian data to little-endian IO registers. Fix this by using the readl and writel relaxed versions which ensure little endian IO. Signed-off-by: Ben Dooks --- arch/arm/mach-exynos/firmware.c | 16 ++++++++-------- arch/arm/mach-exynos/headsmp.S | 3 +++ arch/arm/mach-exynos/platsmp.c | 4 ++-- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 1bfd1b0..96b5e92 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -41,9 +41,9 @@ static int exynos_do_idle(unsigned long mode) case FW_DO_IDLE_AFTR: if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) exynos_save_cp15(); - __raw_writel(virt_to_phys(exynos_cpu_resume_ns), + writel_relaxed(virt_to_phys(exynos_cpu_resume_ns), sysram_ns_base_addr + 0x24); - __raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20); + writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20); if (soc_is_exynos3250()) { flush_cache_all(); exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE, @@ -97,7 +97,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) if (soc_is_exynos4412()) boot_reg += 4 * cpu; - __raw_writel(boot_addr, boot_reg); + writel_relaxed(boot_addr, boot_reg); return 0; } @@ -113,7 +113,7 @@ static int exynos_get_cpu_boot_addr(int cpu, unsigned long *boot_addr) if (soc_is_exynos4412()) boot_reg += 4 * cpu; - *boot_addr = __raw_readl(boot_reg); + *boot_addr = readl_relaxed(boot_reg); return 0; } @@ -234,20 +234,20 @@ void exynos_set_boot_flag(unsigned int cpu, unsigned int mode) { unsigned int tmp; - tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4); + tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4); if (mode & BOOT_MODE_MASK) tmp &= ~BOOT_MODE_MASK; tmp |= mode; - __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4); + writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4); } void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode) { unsigned int tmp; - tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4); + tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4); tmp &= ~mode; - __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4); + writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4); } diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S index b54f970..d3d24ab 100644 --- a/arch/arm/mach-exynos/headsmp.S +++ b/arch/arm/mach-exynos/headsmp.S @@ -12,12 +12,15 @@ #include #include +#include + /* * exynos4 specific entry point for secondary CPUs. This provides * a "holding pen" into which all secondary cores are held until we're * ready for them to initialise. */ ENTRY(exynos4_secondary_startup) +ARM_BE8(setend be) mrc p15, 0, r0, c0, c0, 5 and r0, r0, #15 adr r4, 1f diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 85c3be6..98ffe1e 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -264,7 +264,7 @@ int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr) ret = PTR_ERR(boot_reg); goto fail; } - __raw_writel(boot_addr, boot_reg); + writel_relaxed(boot_addr, boot_reg); ret = 0; } fail: @@ -289,7 +289,7 @@ int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr) ret = PTR_ERR(boot_reg); goto fail; } - *boot_addr = __raw_readl(boot_reg); + *boot_addr = readl_relaxed(boot_reg); ret = 0; } fail: