From patchwork Wed Dec 28 10:34:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaehoon Chung X-Patchwork-Id: 9490143 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 801BD60838 for ; Wed, 28 Dec 2016 10:35:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 658E920855 for ; Wed, 28 Dec 2016 10:35:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5943B2624D; Wed, 28 Dec 2016 10:35:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8056220855 for ; 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Wed, 28 Dec 2016 10:34:55 +0000 (GMT) X-AuditID: b6c32a58-f79726d000001ac1-d4-586395500f1e Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id A2.BD.28332.F4593685; Wed, 28 Dec 2016 19:34:55 +0900 (KST) Received: from localhost.localdomain ([10.113.62.216]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OIW00D915E6UG10@mmp2.samsung.com>; Wed, 28 Dec 2016 19:34:55 +0900 (KST) From: Jaehoon Chung To: linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, kgene@kernel.org, krzk@kernel.org, kishon@ti.com, jingoohan1@gmail.com, vivek.gautam@codeaurora.org, pankaj.dubey@samsung.com, alim.akhtar@samsung.com, cpgs@samsung.com, Jaehoon Chung Subject: [PATCH 3/4] Documetation: binding: modify the exynos5440 pcie binding Date: Wed, 28 Dec 2016 19:34:53 +0900 Message-id: <20161228103454.26467-4-jh80.chung@samsung.com> X-Mailer: git-send-email 2.10.2 In-reply-to: <20161228103454.26467-1-jh80.chung@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrFKsWRmVeSWpSXmKPExsWy7bCmpm7A1OQIgznrmS0ezNvGZrGkKcPi 5SFNi/lHzrFa3PjVxmqx4stMdov+x6+ZLS487WGzOH9+A7vF5V1z2CzOzjvOZjHj/D4mi6XX LzJZLNr6hd2ide8RdosTP3cwOwh4rJm3htHjcl8vk8fOWXfZPRZsKvXYtKqTzaNvyypGj+M3 tjN5fN4kF8ARlWqTkZqYklqkkJqXnJ+SmZduq+QdHO8cb2pmYKhraGlhrqSQl5ibaqvk4hOg 65aZA3S/kkJZYk4pUCggsbhYSd/Opii/tCRVISO/uMRWKdrQ0EjP0MBcz8jISM/EONbKyBSo JCE1Y/6XXuaCF5IVW/83MjYwPhfpYuTkkBAwkZh0chI7hC0mceHeerYuRi4OIYGljBJrj99l AkkICbQzSbStCoFpeDR/DzNE0RxGiauL/kB1/GCUmLb4CBtIFZuAjsT2b8fBukUEZCU+Xt4D VsQs8ItJ4sC+D0AJDg5hgQCJH1dKQWpYBFQl3h7qZQWxeQWsJb6sn8oGsU1eYuH5I2BzOAVs JJ5fOAQ2R0LgGLvEz679bCBzJIAWbDrADFHvInFwy0aod4QlXh3fAmVLS/xdeosRorebUeLf l41Qg3oYJW5tXc0EUWUscf/BPbBJzAJ8Er2/nzBBLOCV6GgTgijxkGj6/osVwnaU+Ld/LTQo +hklbmx4wjKBUWYBI8MqRrHUguLc9NRi0wITveLE3OLSvHS95PzcTYzgdKcVsYPx34ygQ4wC HIxKPLwB15IihFgTy4orcw8xSnAwK4nw7p+YHCHEm5JYWZValB9fVJqTWnyI0RQYUBOZpUST 84GpOK8k3tDEzNDEyBIIzQ3NlcR5F1RYRwgJpCeWpGanphakFsH0MXFwSjUwZmqwpj9y6LBQ OvBt5eY907bMvL5W+9u9vtkXM2YvyxJi/FL5WPHxlmedikLb/ntVRCySfH7haBaPxNQzPrZ6 a450z1xxOtr75M6ijAff+m9K3F5fscFiz68JqZ8n58sLqX15vXnL5/jXm+6KCMxdHsugnv7j zaVZGzvE2lpZ/sae28c8c2ecl5cSS3FGoqEWc1FxIgBfPhmCjQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrGIsWRmVeSWpSXmKPExsVy+t9jQV3/qckRBr+/GVg8mLeNzWJJU4bF y0OaFvOPnGO1uPGrjdVixZeZ7Bb9j18zW1x42sNmcf78BnaLy7vmsFmcnXeczWLG+X1MFkuv X2SyWLT1C7tF694j7BYnfu5gdhDwWDNvDaPH5b5eJo+ds+6yeyzYVOqxaVUnm0ffllWMHsdv bGfy+LxJLoAjys0mIzUxJbVIITUvOT8lMy/dVik0xE3XQkkhLzE31VYpQtc3JEhJoSwxpxTI MzJAAw7OAe7BSvp2CW4Z87/0Mhe8kKzY+r+RsYHxuUgXIyeHhICJxKP5e5ghbDGJC/fWs3Ux cnEICcxilPh1fzk7hPODUeLv+S5GkCo2AR2J7d+OM4HYIgKyEh8v72EDsZkFfjFJLN1nCmIL C/hJtPftA6thEVCVeHuolxXE5hWwlviyfiobxDZ5iYXnj4DVcArYSDy/cAgsLgRU03XzLeME Rt4FjAyrGCVSC5ILipPSc43yUsv1ihNzi0vz0vWS83M3MYLj6Jn0DsbDu9wPMQpwMCrx8AZc S4oQYk0sK67MPcQowcGsJMK7f2JyhBBvSmJlVWpRfnxRaU5q8SFGU6DDJjJLiSbnA2M8ryTe 0MTcxNzYwMLc0tLESEmct3H2s3AhgfTEktTs1NSC1CKYPiYOTqkGRtUQ92X79PMtXkx+uj81 79Bfpl/xlSYiW9atzTm3+B2TzOrHbcdPH1zc224YFPvC9CpjSoqs4xyOjKN/Fla1d/ZfTFpg 0aTMtqkq78yyN335j3+Wy564WXk/Jy17hR6n6KUJjYKr1IP/zTpTHHusrUneNU731yLv7q4d Z/6f2aTwiyG248O3h0osxRmJhlrMRcWJANGIDwy5AgAA X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20161228103455epcas5p2b3ea563efc00c776e77477ab3c778bb1 X-Msg-Generator: CA X-Sender-IP: 203.254.230.27 X-Local-Sender: =?UTF-8?B?7KCV7J6s7ZuIG1RpemVuIFBsYXRmb3JtIExhYihTL1fshLw=?= =?UTF-8?B?7YSwKRvsgrzshLHsoITsnpAbUzUo7LGF7J6EKS/ssYXsnoQ=?= X-Global-Sender: =?UTF-8?B?SmFlaG9vbiBDaHVuZxtUaXplbiBQbGF0Zm9ybSBMYWIuG1Nh?= =?UTF-8?B?bXN1bmcgRWxlY3Ryb25pY3MbUzUvU2VuaW9yIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG1NUQUYbQzEwVjgxMTE=?= CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-HopCount: 7 X-CMS-RootMailID: 20161228103455epcas5p2b3ea563efc00c776e77477ab3c778bb1 X-RootMTR: 20161228103455epcas5p2b3ea563efc00c776e77477ab3c778bb1 References: <20161228103454.26467-1-jh80.chung@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to using PHY framework, modified the exynos5440-pcie binding. And use "config" property to follow the designware-pcie binding. Signed-off-by: Jaehoon Chung --- .../bindings/pci/samsung,exynos5440-pcie.txt | 29 +++++++++++++--------- 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt index 4f9d23d..51f6214 100644 --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt +++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt @@ -5,10 +5,15 @@ and thus inherits all the common properties defined in designware-pcie.txt. Required properties: - compatible: "samsung,exynos5440-pcie" -- reg: base addresses and lengths of the pcie controller, - the phy controller, additional register for the phy controller. +- reg: base addresses and lengths of the pcie controller - interrupts: A list of interrupt outputs for level interrupt, pulse interrupt, special interrupt. +- phys: From PHY binding. Phandle for the Generic PHY. + Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt +- phy-names: Must be "pcie-phy". + +Other common properties refer to + Documentation/devicetree/binding/pci/designware-pcie.txt Example: @@ -16,18 +21,18 @@ SoC specific DT Entry: pcie@290000 { compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x290000 0x1000 - 0x270000 0x1000 - 0x271000 0x40>; + reg = <0x290000 0x1000>, <0x40000000 0x100>; + reg-names = "elbi", "config"; interrupts = <0 20 0>, <0 21 0>, <0 22 0>; clocks = <&clock 28>, <&clock 27>; clock-names = "pcie", "pcie_bus"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ - 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ + ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ + phys = <&pcie_phy0>; + phy-names = "pcie-phy"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; @@ -36,17 +41,17 @@ SoC specific DT Entry: pcie@2a0000 { compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x2a0000 0x1000 - 0x272000 0x1000 - 0x271040 0x40>; + reg = <0x2a0000 0x1000>, <0x60000000 0x1000>; + reg-names = "elbi", "config"; interrupts = <0 23 0>, <0 24 0>, <0 25 0>; clocks = <&clock 29>, <&clock 27>; clock-names = "pcie", "pcie_bus"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ - 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ + phys = <&pcie_phy1>; + phy-names = "pcie-phy"; + ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>;