From patchwork Fri Jan 27 20:05:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 9542603 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B3E62604AB for ; Fri, 27 Jan 2017 20:23:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A4FEB26E91 for ; Fri, 27 Jan 2017 20:23:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 99EC027F93; Fri, 27 Jan 2017 20:23:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EE9BA26E91 for ; Fri, 27 Jan 2017 20:23:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751309AbdA0UFv (ORCPT ); Fri, 27 Jan 2017 15:05:51 -0500 Received: from mail.kernel.org ([198.145.29.136]:43312 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751305AbdA0UFt (ORCPT ); Fri, 27 Jan 2017 15:05:49 -0500 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 797FA20444; Fri, 27 Jan 2017 20:05:47 +0000 (UTC) Received: from localhost.localdomain (bzq-79-177-55-173.red.bezeqint.net [79.177.55.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id F1E6E20498; Fri, 27 Jan 2017 20:05:42 +0000 (UTC) From: Krzysztof Kozlowski To: Marek Szyprowski , Kishon Vijay Abraham I , Kukjin Kim , Krzysztof Kozlowski , Javier Martinez Canillas , Lee Jones , Sylwester Nawrocki , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 4/4] phy: exynos: Use one define for enable bit Date: Fri, 27 Jan 2017 22:05:10 +0200 Message-Id: <20170127200510.4444-5-krzk@kernel.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170127200510.4444-1-krzk@kernel.org> References: <20170127200510.4444-1-krzk@kernel.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There is no need for separate defines for Exynos4 and Exynos5 phy enable bit and MIPI phy reset bits. In both cases there are the same so simplify it. This reduces number of defines and allows removal of one header file. Signed-off-by: Krzysztof Kozlowski Acked-by: Lee Jones --- drivers/phy/phy-exynos-dp-video.c | 5 ++-- drivers/phy/phy-exynos-mipi-video.c | 39 ++++++++++++++--------------- drivers/phy/phy-exynos5-usbdrd.c | 5 ++-- include/linux/mfd/syscon/exynos5-pmu.h | 24 ------------------ include/linux/soc/samsung/exynos-regs-pmu.h | 3 ++- 5 files changed, 25 insertions(+), 51 deletions(-) delete mode 100644 include/linux/mfd/syscon/exynos5-pmu.h diff --git a/drivers/phy/phy-exynos-dp-video.c b/drivers/phy/phy-exynos-dp-video.c index d72193188980..bb3279dbf88c 100644 --- a/drivers/phy/phy-exynos-dp-video.c +++ b/drivers/phy/phy-exynos-dp-video.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -37,7 +36,7 @@ static int exynos_dp_video_phy_power_on(struct phy *phy) /* Disable power isolation on DP-PHY */ return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset, - EXYNOS5_PHY_ENABLE, EXYNOS5_PHY_ENABLE); + EXYNOS4_PHY_ENABLE, EXYNOS4_PHY_ENABLE); } static int exynos_dp_video_phy_power_off(struct phy *phy) @@ -46,7 +45,7 @@ static int exynos_dp_video_phy_power_off(struct phy *phy) /* Enable power isolation on DP-PHY */ return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset, - EXYNOS5_PHY_ENABLE, 0); + EXYNOS4_PHY_ENABLE, 0); } static const struct phy_ops exynos_dp_video_phy_ops = { diff --git a/drivers/phy/phy-exynos-mipi-video.c b/drivers/phy/phy-exynos-mipi-video.c index acef1d92691e..c198886f80a3 100644 --- a/drivers/phy/phy-exynos-mipi-video.c +++ b/drivers/phy/phy-exynos-mipi-video.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -64,7 +63,7 @@ static const struct mipi_phy_device_desc s5pv210_mipi_phy = { { /* EXYNOS_MIPI_PHY_ID_CSIS0 */ .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0, - .enable_val = EXYNOS4_MIPI_PHY_ENABLE, + .enable_val = EXYNOS4_PHY_ENABLE, .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0), .enable_map = EXYNOS_MIPI_REGMAP_PMU, .resetn_val = EXYNOS4_MIPI_PHY_SRESETN, @@ -73,7 +72,7 @@ static const struct mipi_phy_device_desc s5pv210_mipi_phy = { }, { /* EXYNOS_MIPI_PHY_ID_DSIM0 */ .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0, - .enable_val = EXYNOS4_MIPI_PHY_ENABLE, + .enable_val = EXYNOS4_PHY_ENABLE, .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0), .enable_map = EXYNOS_MIPI_REGMAP_PMU, .resetn_val = EXYNOS4_MIPI_PHY_MRESETN, @@ -82,7 +81,7 @@ static const struct mipi_phy_device_desc s5pv210_mipi_phy = { }, { /* EXYNOS_MIPI_PHY_ID_CSIS1 */ .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1, - .enable_val = EXYNOS4_MIPI_PHY_ENABLE, + .enable_val = EXYNOS4_PHY_ENABLE, .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1), .enable_map = EXYNOS_MIPI_REGMAP_PMU, .resetn_val = EXYNOS4_MIPI_PHY_SRESETN, @@ -91,7 +90,7 @@ static const struct mipi_phy_device_desc s5pv210_mipi_phy = { }, { /* EXYNOS_MIPI_PHY_ID_DSIM1 */ .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1, - .enable_val = EXYNOS4_MIPI_PHY_ENABLE, + .enable_val = EXYNOS4_PHY_ENABLE, .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1), .enable_map = EXYNOS_MIPI_REGMAP_PMU, .resetn_val = EXYNOS4_MIPI_PHY_MRESETN, @@ -109,46 +108,46 @@ static const struct mipi_phy_device_desc exynos5420_mipi_phy = { { /* EXYNOS_MIPI_PHY_ID_CSIS0 */ .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0, - .enable_val = EXYNOS5_PHY_ENABLE, + .enable_val = EXYNOS4_PHY_ENABLE, .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0), .enable_map = EXYNOS_MIPI_REGMAP_PMU, - .resetn_val = EXYNOS5_MIPI_PHY_S_RESETN, + .resetn_val = EXYNOS4_MIPI_PHY_SRESETN, .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0), .resetn_map = EXYNOS_MIPI_REGMAP_PMU, }, { /* EXYNOS_MIPI_PHY_ID_DSIM0 */ .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0, - .enable_val = EXYNOS5_PHY_ENABLE, + .enable_val = EXYNOS4_PHY_ENABLE, .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0), .enable_map = EXYNOS_MIPI_REGMAP_PMU, - .resetn_val = EXYNOS5_MIPI_PHY_M_RESETN, + .resetn_val = EXYNOS4_MIPI_PHY_MRESETN, .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0), .resetn_map = EXYNOS_MIPI_REGMAP_PMU, }, { /* EXYNOS_MIPI_PHY_ID_CSIS1 */ .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1, - .enable_val = EXYNOS5_PHY_ENABLE, + .enable_val = EXYNOS4_PHY_ENABLE, .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1), .enable_map = EXYNOS_MIPI_REGMAP_PMU, - .resetn_val = EXYNOS5_MIPI_PHY_S_RESETN, + .resetn_val = EXYNOS4_MIPI_PHY_SRESETN, .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1), .resetn_map = EXYNOS_MIPI_REGMAP_PMU, }, { /* EXYNOS_MIPI_PHY_ID_DSIM1 */ .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1, - .enable_val = EXYNOS5_PHY_ENABLE, + .enable_val = EXYNOS4_PHY_ENABLE, .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1), .enable_map = EXYNOS_MIPI_REGMAP_PMU, - .resetn_val = EXYNOS5_MIPI_PHY_M_RESETN, + .resetn_val = EXYNOS4_MIPI_PHY_MRESETN, .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1), .resetn_map = EXYNOS_MIPI_REGMAP_PMU, }, { /* EXYNOS_MIPI_PHY_ID_CSIS2 */ .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE, - .enable_val = EXYNOS5_PHY_ENABLE, + .enable_val = EXYNOS4_PHY_ENABLE, .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(2), .enable_map = EXYNOS_MIPI_REGMAP_PMU, - .resetn_val = EXYNOS5_MIPI_PHY_S_RESETN, + .resetn_val = EXYNOS4_MIPI_PHY_SRESETN, .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(2), .resetn_map = EXYNOS_MIPI_REGMAP_PMU, }, @@ -172,7 +171,7 @@ static const struct mipi_phy_device_desc exynos5433_mipi_phy = { { /* EXYNOS_MIPI_PHY_ID_CSIS0 */ .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0, - .enable_val = EXYNOS5_PHY_ENABLE, + .enable_val = EXYNOS4_PHY_ENABLE, .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0), .enable_map = EXYNOS_MIPI_REGMAP_PMU, .resetn_val = BIT(0), @@ -181,7 +180,7 @@ static const struct mipi_phy_device_desc exynos5433_mipi_phy = { }, { /* EXYNOS_MIPI_PHY_ID_DSIM0 */ .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0, - .enable_val = EXYNOS5_PHY_ENABLE, + .enable_val = EXYNOS4_PHY_ENABLE, .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0), .enable_map = EXYNOS_MIPI_REGMAP_PMU, .resetn_val = BIT(0), @@ -190,7 +189,7 @@ static const struct mipi_phy_device_desc exynos5433_mipi_phy = { }, { /* EXYNOS_MIPI_PHY_ID_CSIS1 */ .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE, - .enable_val = EXYNOS5_PHY_ENABLE, + .enable_val = EXYNOS4_PHY_ENABLE, .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1), .enable_map = EXYNOS_MIPI_REGMAP_PMU, .resetn_val = BIT(1), @@ -199,7 +198,7 @@ static const struct mipi_phy_device_desc exynos5433_mipi_phy = { }, { /* EXYNOS_MIPI_PHY_ID_DSIM1 */ .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE, - .enable_val = EXYNOS5_PHY_ENABLE, + .enable_val = EXYNOS4_PHY_ENABLE, .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1), .enable_map = EXYNOS_MIPI_REGMAP_PMU, .resetn_val = BIT(1), @@ -208,7 +207,7 @@ static const struct mipi_phy_device_desc exynos5433_mipi_phy = { }, { /* EXYNOS_MIPI_PHY_ID_CSIS2 */ .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE, - .enable_val = EXYNOS5_PHY_ENABLE, + .enable_val = EXYNOS4_PHY_ENABLE, .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(2), .enable_map = EXYNOS_MIPI_REGMAP_PMU, .resetn_val = BIT(0), diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c index 7c896d0cda18..7c41daa2c625 100644 --- a/drivers/phy/phy-exynos5-usbdrd.c +++ b/drivers/phy/phy-exynos5-usbdrd.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -236,10 +235,10 @@ static void exynos5_usbdrd_phy_isol(struct phy_usb_instance *inst, if (!inst->reg_pmu) return; - val = on ? 0 : EXYNOS5_PHY_ENABLE; + val = on ? 0 : EXYNOS4_PHY_ENABLE; regmap_update_bits(inst->reg_pmu, inst->pmu_offset, - EXYNOS5_PHY_ENABLE, val); + EXYNOS4_PHY_ENABLE, val); } /* diff --git a/include/linux/mfd/syscon/exynos5-pmu.h b/include/linux/mfd/syscon/exynos5-pmu.h deleted file mode 100644 index 6108857ffcca..000000000000 --- a/include/linux/mfd/syscon/exynos5-pmu.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Exynos5 SoC series Power Management Unit (PMU) register offsets - * and bit definitions. - * - * Copyright (C) 2014 Samsung Electronics Co., Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ -#define _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ - -/* Exynos5 PMU register definitions */ - -/* Exynos5250 specific register definitions */ - -/* Exynos5420 specific register definitions */ - -#define EXYNOS5_PHY_ENABLE BIT(0) -#define EXYNOS5_MIPI_PHY_S_RESETN BIT(1) -#define EXYNOS5_MIPI_PHY_M_RESETN BIT(2) -#endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */ diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h index 6dbd65012ccd..b7e961a7a43a 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -52,7 +52,8 @@ /* MIPI_PHYn_CONTROL, valid for Exynos3250, Exynos4, Exynos5250 and Exynos5433 */ #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4) -#define EXYNOS4_MIPI_PHY_ENABLE (1 << 0) +/* Phy enable bit, common for all phy registers, not only MIPI */ +#define EXYNOS4_PHY_ENABLE (1 << 0) #define EXYNOS4_MIPI_PHY_SRESETN (1 << 1) #define EXYNOS4_MIPI_PHY_MRESETN (1 << 2) #define EXYNOS4_MIPI_PHY_RESET_MASK (3 << 1)