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Wed, 11 Oct 2017 09:25:20 +0000 (GMT) X-AuditID: cbfec7f2-f793b6d000003243-ee-59dde3815437 Received: from eusync4.samsung.com ( [203.254.199.214]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id CD.FD.20118.083EDD95; Wed, 11 Oct 2017 10:25:20 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OXN00BGOJI4PG80@eusync4.samsung.com>; Wed, 11 Oct 2017 10:25:20 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Chanwoo Choi , Inki Dae , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH v3 1/5] clk: samsung: Instantiate Exynos4412 ISP clocks only when available Date: Wed, 11 Oct 2017 11:25:11 +0200 Message-id: <20171011092515.1698-2-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.14.2 In-reply-to: <20171011092515.1698-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrBIsWRmVeSWpSXmKPExsWy7djP87qNj+9GGuzs4rHYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6Mrf/nMBWcUqw41LibrYHxuEwXIyeHhICJxP6tC5ggbDGJC/fWs3UxcnEI CSxllLj5t4MFwvnMKPGx7z8bTMfv83vBbCGBZYwSZ/pkIIoamCQu3DnECpJgEzCU6HrbBVYk IuAg8fnTa0aQImaBNiaJswf2g+0TFoiVWPp3JVgRi4CqxLFJDewgNq+AjcT926/YIbbJS7xf cJ8RxOYUsJV49aIN7D4JgQ42iZNfVrFCFLlIrJh5E+o8YYlXx7dANctIXJ7czQJh9zNKNLVq Q9gzGCXOveWFsK0lDh+/CDaHWYBPYtK26cxdjBxAcV6JjjYhiBIPiT8NS6DGOEocuraLBeL7 CYwSKx/aTGCUXsDIsIpRJLW0ODc9tdhYrzgxt7g0L10vOT93EyMwPk//O/5pB+PXE1aHGAU4 GJV4eC/U340UYk0sK67MPcQowcGsJMJ77gZQiDclsbIqtSg/vqg0J7X4EKM0B4uSOK9tVFuk kEB6YklqdmpqQWoRTJaJg1OqgTE6rf3Ajf3mJ75mzMq86n1UxXHPkU1KAfahc7h+xf+Y9VJz WlSDj1jNia0PXHdtdD6kt/Wu/ofld3NvtuVFJxU0tOSfP59/aMfr9l29RafmX+p5bMN+qpOD 15I1Yp3Z02yH7wc5J5pcfbPQOH29TkSizM/LrN8rZT4+N9Mz/xpQyZi/ZOU0QWclluKMREMt 5qLiRACSo+nnywIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnluLIzCtJLcpLzFFi42I5/e/4Nd2Gx3cjDbY/NbDYOGM9q8X1L89Z LSbdn8Bicf78BnaLjz33WC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6Mrf/nMBWcUqw41LibrYHxuEwXIyeHhICJxO/ze9kgbDGJC/fWA9lcHEIC SxglblyfywzhNDFJLN54kwWkik3AUKLrbRdYh4iAg8TnT68ZQYqYBTqYJPbsfQiWEBaIlVj6 dyWYzSKgKnFsUgM7iM0rYCNx//Yrdoh18hLvF9xnBLE5BWwlXr1oA6sXAqp5vm0b2wRG3gWM DKsYRVJLi3PTc4uN9IoTc4tL89L1kvNzNzECg2nbsZ9bdjB2vQs+xCjAwajEwytw/U6kEGti WXFl7iFGCQ5mJRHeczfuRgrxpiRWVqUW5ccXleakFh9ilOZgURLn7d2zOlJIID2xJDU7NbUg tQgmy8TBKdXAOHnaWYdKK+fZ/hFmVYInrs6y/7pkQVBsfJHNtybNpBVym8y2fnqZXaZsd9N1 /qkNgjvabN5/fdzwZsXZ/zbt81nurthxlUk68dUqlbB8iTt5dambOpuyp8jzKu6/cFTjwC7+ KadXzHi+fGe0j4NUwmOPj9fqufiX/epib81ibQnmSDmoPUPmjRJLcUaioRZzUXEiACttcXci AgAA X-CMS-MailID: 20171011092520eucas1p2a86dcd52a7c0c4b329563e5eaad3fd76 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-CMS-RootMailID: 20171011092520eucas1p2a86dcd52a7c0c4b329563e5eaad3fd76 X-RootMTR: 20171011092520eucas1p2a86dcd52a7c0c4b329563e5eaad3fd76 References: <20171011092515.1698-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some registers for the Exynos 4412 ISP (Camera subsystem) clocks are located in the ISP power domain. Istatiate those clocks only when provided clock registers resource covers those registers. This is a preparation for adding a separate clock driver for ISP clocks, which will be intergated with power domain using runtime PM feature. Signed-off-by: Marek Szyprowski Acked-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos4.c | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index e40b77583c47..bdd68247e054 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -822,6 +822,12 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), + DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), + DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3), + DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), +}; + +static struct samsung_div_clock exynos4x12_isp_div_clks[] = { DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, CLK_GET_RATE_NOCACHE, 0), DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, @@ -831,9 +837,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { 4, 3, CLK_GET_RATE_NOCACHE, 0), DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3, CLK_GET_RATE_NOCACHE, 0), - DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), - DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3), - DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), }; /* list of gate clocks supported in all exynos4 soc's */ @@ -1132,6 +1135,13 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { 0, 0), GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, 0, 0), + GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), + GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0), + GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, + 0), +}; + +static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = { GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, @@ -1184,10 +1194,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), - GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), - GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0), - GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, - 0), }; static const struct samsung_clock_alias exynos4_aliases[] __initconst = { @@ -1522,6 +1528,8 @@ static void __init exynos4_clk_init(struct device_node *np, e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d), CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); } else { + struct resource res; + samsung_clk_register_mux(ctx, exynos4x12_mux_clks, ARRAY_SIZE(exynos4x12_mux_clks)); samsung_clk_register_div(ctx, exynos4x12_div_clks, @@ -1533,6 +1541,15 @@ static void __init exynos4_clk_init(struct device_node *np, samsung_clk_register_fixed_factor(ctx, exynos4x12_fixed_factor_clks, ARRAY_SIZE(exynos4x12_fixed_factor_clks)); + + of_address_to_resource(np, 0, &res); + if (resource_size(&res) > 0x18000) { + samsung_clk_register_div(ctx, exynos4x12_isp_div_clks, + ARRAY_SIZE(exynos4x12_isp_div_clks)); + samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks, + ARRAY_SIZE(exynos4x12_isp_gate_clks)); + } + if (of_machine_is_compatible("samsung,exynos4412")) { exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,