diff mbox

[1/7] clk: samsung: exynos3250: fix PLL rates

Message ID 20180213134032.30235-2-a.hajda@samsung.com (mailing list archive)
State Not Applicable
Headers show

Commit Message

Andrzej Hajda Feb. 13, 2018, 1:40 p.m. UTC
Declared rates did not match rates generated by PLL.
As a result driver behaved inconsitently.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
---
 drivers/clk/samsung/clk-exynos3250.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Krzysztof Kozlowski Feb. 13, 2018, 2:41 p.m. UTC | #1
On Tue, Feb 13, 2018 at 2:40 PM, Andrzej Hajda <a.hajda@samsung.com> wrote:
> Declared rates did not match rates generated by PLL.
> As a result driver behaved inconsitently.
>
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos3250.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

How about marking these cc-stable and adding fixes tag?

Best regards,
Krzysztof
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Chanwoo Choi Feb. 14, 2018, 5:03 a.m. UTC | #2
On 2018년 02월 13일 22:40, Andrzej Hajda wrote:
> Declared rates did not match rates generated by PLL.
> As a result driver behaved inconsitently.
> 
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos3250.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
> index 1b81e283f605..ed36728424a2 100644
> --- a/drivers/clk/samsung/clk-exynos3250.c
> +++ b/drivers/clk/samsung/clk-exynos3250.c
> @@ -698,7 +698,7 @@ static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst =
>  	PLL_36XX_RATE(144000000,  96, 2, 3,     0),
>  	PLL_36XX_RATE( 96000000, 128, 2, 4,     0),
>  	PLL_36XX_RATE( 84000000, 112, 2, 4,     0),
> -	PLL_36XX_RATE( 80000004, 106, 2, 4, 43691),
> +	PLL_36XX_RATE( 80000003, 106, 2, 4, 43691),
>  	PLL_36XX_RATE( 73728000,  98, 2, 4, 19923),
>  	PLL_36XX_RATE( 67737598, 270, 3, 5, 62285),
>  	PLL_36XX_RATE( 65535999, 174, 2, 5, 49982),
> @@ -734,7 +734,7 @@ static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst =
>  	PLL_36XX_RATE(148352005,  98, 2, 3, 59070),
>  	PLL_36XX_RATE(108000000, 144, 2, 4,     0),
>  	PLL_36XX_RATE( 74250000,  99, 2, 4,     0),
> -	PLL_36XX_RATE( 74176002,  98, 3, 4, 59070),
> +	PLL_36XX_RATE( 74176002,  98, 2, 4, 59070),
>  	PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),
>  	PLL_36XX_RATE( 54000000, 144, 2, 5,     0),
>  	{ /* sentinel */ }
> 

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Sylwester Nawrocki Feb. 16, 2018, 10 a.m. UTC | #3
On 02/13/2018 03:41 PM, Krzysztof Kozlowski wrote:
> On Tue, Feb 13, 2018 at 2:40 PM, Andrzej Hajda <a.hajda@samsung.com> wrote:
>> Declared rates did not match rates generated by PLL.
>> As a result driver behaved inconsitently.
>>
>> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
>> ---
>>  drivers/clk/samsung/clk-exynos3250.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> How about marking these cc-stable and adding fixes tag?

It may potentially cause regressions so I would rather not back port it 
to older kernels. This applies to all patches in this series, except 7/7.
Krzysztof Kozlowski Feb. 16, 2018, 10:06 a.m. UTC | #4
On Fri, Feb 16, 2018 at 11:00 AM, Sylwester Nawrocki
<s.nawrocki@samsung.com> wrote:
> On 02/13/2018 03:41 PM, Krzysztof Kozlowski wrote:
>> On Tue, Feb 13, 2018 at 2:40 PM, Andrzej Hajda <a.hajda@samsung.com> wrote:
>>> Declared rates did not match rates generated by PLL.
>>> As a result driver behaved inconsitently.
>>>
>>> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
>>> ---
>>>  drivers/clk/samsung/clk-exynos3250.c | 4 ++--
>>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> How about marking these cc-stable and adding fixes tag?
>
> It may potentially cause regressions so I would rather not back port it
> to older kernels. This applies to all patches in this series, except 7/7.

Hm, existing (old) values were more-or-less tested already, so indeed
sounds reasonable.

BR,
Krzysztof
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Sylwester Nawrocki Feb. 16, 2018, 11:58 a.m. UTC | #5
On 02/13/2018 02:40 PM, Andrzej Hajda wrote:
> Declared rates did not match rates generated by PLL.
> As a result driver behaved inconsitently.

How about changing commit message to something along the lines of:

"Rates declared in PLL rate tables should match exactly rates calculated
from PLL coefficients. If that is not the case, rate of parent might be being
set not as expected.  For instance, if in the PLL rates table we have
a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate 
callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate
will return 393216003.  If we now attempt to set rate of a PLL's child divider 
clock to 393216000/2 its rate will be 131072001, rather than 196608000.
That is the divider will be set to 3 instead of 2, because 393216003/2 is
greater than 196608000.

To fix this issue declared rates are changed to exactly match rates generated 
by a PLL, as calculated from the P, M, S, K coefficients.

In this patch an erroneous P value for 74176002 output frequency is also 
corrected."

I would do this also for patches 2...6/7 before applying.

--
Thanks,
Sylwester
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Sylwester Nawrocki Feb. 16, 2018, 12:03 p.m. UTC | #6
On 02/16/2018 12:58 PM, Sylwester Nawrocki wrote:
> On 02/13/2018 02:40 PM, Andrzej Hajda wrote:
>> Declared rates did not match rates generated by PLL.
>> As a result driver behaved inconsitently.
> 
> How about changing commit message to something along the lines of:
> 
> "Rates declared in PLL rate tables should match exactly rates calculated
> from PLL coefficients. If that is not the case, rate of parent might be being

s/parent/PLL's child clock

> set not as expected.  For instance, if in the PLL rates table we have
> a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate 
> callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate
> will return 393216003.  If we now attempt to set rate of a PLL's child divider 
> clock to 393216000/2 its rate will be 131072001, rather than 196608000.
> That is the divider will be set to 3 instead of 2, because 393216003/2 is
> greater than 196608000.
> 
> To fix this issue declared rates are changed to exactly match rates generated 
> by a PLL, as calculated from the P, M, S, K coefficients.
> 
> In this patch an erroneous P value for 74176002 output frequency is also 
> corrected.
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diff mbox

Patch

diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index 1b81e283f605..ed36728424a2 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -698,7 +698,7 @@  static const struct samsung_pll_rate_table exynos3250_epll_rates[] __initconst =
 	PLL_36XX_RATE(144000000,  96, 2, 3,     0),
 	PLL_36XX_RATE( 96000000, 128, 2, 4,     0),
 	PLL_36XX_RATE( 84000000, 112, 2, 4,     0),
-	PLL_36XX_RATE( 80000004, 106, 2, 4, 43691),
+	PLL_36XX_RATE( 80000003, 106, 2, 4, 43691),
 	PLL_36XX_RATE( 73728000,  98, 2, 4, 19923),
 	PLL_36XX_RATE( 67737598, 270, 3, 5, 62285),
 	PLL_36XX_RATE( 65535999, 174, 2, 5, 49982),
@@ -734,7 +734,7 @@  static const struct samsung_pll_rate_table exynos3250_vpll_rates[] __initconst =
 	PLL_36XX_RATE(148352005,  98, 2, 3, 59070),
 	PLL_36XX_RATE(108000000, 144, 2, 4,     0),
 	PLL_36XX_RATE( 74250000,  99, 2, 4,     0),
-	PLL_36XX_RATE( 74176002,  98, 3, 4, 59070),
+	PLL_36XX_RATE( 74176002,  98, 2, 4, 59070),
 	PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),
 	PLL_36XX_RATE( 54000000, 144, 2, 5,     0),
 	{ /* sentinel */ }