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However it turned out that having PHY powered is required for proper DRM display pipeline initialization on Peach-Pit Chromebook2 board, as this board freezes otherwise when PHY power off is called in bind. Fix this by keeping PHY powered for the whole bind/unbind driver life cycle. The freeze is probably related to the fact that the display pipeline (Exynos FIMD CTRC -> Exynos/Analogix DP bridge -> PS8625 dp2lvds bridge -> B116XW03 panel) is already configured and enabled by the bootloader and require reset of all components for proper shutdown. Having PHY powered is also needed for proper EDID handling, which initially fixed by commit 510353a63796 ("drm/bridge: analogix dp: Fix runtime PM state in get_modes() callback"). Fixes: f0a8b49c03d2 ("drm/bridge: analogix dp: Fix runtime PM state on driver bind") Signed-off-by: Marek Szyprowski --- drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index b2756bc4225a..42595863cb03 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -1415,7 +1415,6 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev, goto err_disable_pm_runtime; } - phy_power_off(dp->phy); pm_runtime_put(dev); return 0; @@ -1448,6 +1447,7 @@ void analogix_dp_unbind(struct device *dev, struct device *master, drm_dp_aux_unregister(&dp->aux); pm_runtime_disable(dev); + phy_power_off(dp->phy); clk_disable_unprepare(dp->clock); } EXPORT_SYMBOL_GPL(analogix_dp_unbind);