Message ID | 20181018095708.1527-3-m.szyprowski@samsung.com (mailing list archive) |
---|---|
State | Not Applicable |
Headers | show
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Thu, 18 Oct 2018 10:57:16 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0PGS00GLZGZA2H50@eusync3.samsung.com>; Thu, 18 Oct 2018 10:57:16 +0100 (BST) From: Marek Szyprowski <m.szyprowski@samsung.com> To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Marek Szyprowski <m.szyprowski@samsung.com>, Will Deacon <will.deacon@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Marc Zyngier <marc.zyngier@arm.com>, Thomas Gleixner <tglx@linutronix.de>, Daniel Lezcano <daniel.lezcano@linaro.org>, Krzysztof Kozlowski <krzk@kernel.org>, Chanwoo Choi <cw00.choi@samsung.com>, Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>, Inki Dae <inki.dae@samsung.com>, Mark Rutland <mark.rutland@arm.com> Subject: [PATCH v4 2/6] clocksource: exynos_mct: Fix error path in timer resources initialization Date: Thu, 18 Oct 2018 11:57:04 +0200 Message-id: <20181018095708.1527-3-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-reply-to: <20181018095708.1527-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGIsWRmVeSWpSXmKPExsWy7djPc7p/I05EG2yawW2xccZ6Vov3y3oY La5/ec5qMe+zrMWk+xNYLM6f38BusenxNVaLy7vmsFnMOL+PyWLtkbvsFn/v/GOzWHr9IpPF 5k1TmS1efjzB4sDnsWbeGkaPTas62TzuXNvD5vHu3Dl2j81L6j36tqxi9Pi8SS6APYrLJiU1 J7MstUjfLoEr4+eGi+wFX7kq7p7YxdTAOJezi5GTQ0LARGLCq71sILaQwApGidP9Fl2MXED2 Z0aJPS8/McMU3Tzdxw6RWMYocev/YRYIp4FJ4u+GE2DtbAKGEl1vu8BsEYFsic7HDxhBipgF TjJL/Lu5iR0kISyQLHHr3l1WEJtFQFVi84LnTCA2r4CNxO01Vxkh1slLrN5wAGw1p4CtxJn5 78C2SQgcYZP4fPYoG0SRi8SV/jPsELawxKvjW6BsGYnOjoNMEA3NjBLtM2axQzg9jBJb5+yA 6raWOHz8ItgZzAJ8EpO2TQdaxwEU55XoaBOCKPGQmDbvDRvEnxMYJa5sW8w+gVFyASPDKkbx 1NLi3PTUYqO81HK94sTc4tK8dL3k/NxNjMDYPv3v+JcdjLv+JB1iFOBgVOLhfZB6PFqINbGs uDL3EKMEB7OSCG+12YloId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rzL5m2MFhJITyxJzU5NLUgt gskycXBKNTDK6cdzS9V4Vf67uvmi/7tmWYvGtOPHO27Zmp986rYqSyArLOGu2dS+BMk3xUl/ ZRYcPNl+LdOltnHCtQn3g9+VzlQJ8HO32533vE3vYD+P+qTPl+Q9C54GnJR+/Ve5V/2yjc39 dcf83Q+xb1gT0JdQmTF//bM8recH8u7Mqb/wvuXYVKFpR9YrsRRnJBpqMRcVJwIAaGnTcukC AAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrELMWRmVeSWpSXmKPExsVy+t/xq7p/Ik5EG1ybqG2xccZ6Vov3y3oY La5/ec5qMe+zrMWk+xNYLM6f38BusenxNVaLy7vmsFnMOL+PyWLtkbvsFn/v/GOzWHr9IpPF 5k1TmS1efjzB4sDnsWbeGkaPTas62TzuXNvD5vHu3Dl2j81L6j36tqxi9Pi8SS6APYrLJiU1 J7MstUjfLoEr4+eGi+wFX7kq7p7YxdTAOJezi5GTQ0LAROLm6T52EFtIYAmjxL3eqC5GLiC7 iUmia2cjC0iCTcBQouttFxuILSKQLTF/bzc7SBGzwElmiUuP34EVCQskS9y6d5cVxGYRUJXY vOA5E4jNK2AjcXvNVUaIbfISqzccYAaxOQVsJc7Mh+gVAqrp/rOefQIjzwJGhlWMIqmlxbnp ucWGesWJucWleel6yfm5mxiBIbnt2M/NOxgvbQw+xCjAwajEw/sg9Xi0EGtiWXFl7iFGCQ5m JRHearMT0UK8KYmVValF+fFFpTmpxYcYpTlYlMR5zxtURgkJpCeWpGanphakFsFkmTg4pRoY ZdONLE6G+S/kfSnou2mOeSDPJO9XrHmWP+dlZvBduq7+7Y9hcnvOux+P7uUkiP7OkbrMkFye KP1Hf///+ksx0S+tvc89zJjpfF71xZ5E9QDXD6+WOqiutO5kNkg6oSW+IVPbLaVeQVU0vXj3 GV+HXlaeR5t691mrGM1fUr73y4vc8y4J+68osRRnJBpqMRcVJwIAH9crDEUCAAA= X-CMS-MailID: 20181018095716eucas1p103fb0d1a19c6122e885b15526c176967 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20181018095716eucas1p103fb0d1a19c6122e885b15526c176967 References: <20181018095708.1527-1-m.szyprowski@samsung.com> <CGME20181018095716eucas1p103fb0d1a19c6122e885b15526c176967@eucas1p1.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: <linux-samsung-soc.vger.kernel.org> X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP |
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Proper arch timer support for Exynos5433-based TM2(e) boards
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diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index ef18bbf8d20c..49413900b24c 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -561,7 +561,19 @@ static int __init exynos4_timer_resources(struct device_node *np, void __iomem * return 0; out_irq: - free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick); + if (mct_int_type == MCT_INT_PPI) { + free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick); + } else { + for_each_possible_cpu(cpu) { + struct mct_clock_event_device *pcpu_mevt = + per_cpu_ptr(&percpu_mct_tick, cpu); + + if (pcpu_mevt->evt.irq != -1) { + free_irq(pcpu_mevt->evt.irq, pcpu_mevt); + pcpu_mevt->evt.irq = -1; + } + } + } return err; }