From patchwork Mon Jan 28 23:06:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stuart Menefy X-Patchwork-Id: 10785053 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D2AF891E for ; Mon, 28 Jan 2019 23:07:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C2D412B26C for ; Mon, 28 Jan 2019 23:07:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B75CD2B4D0; Mon, 28 Jan 2019 23:07:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 60E542B26C for ; Mon, 28 Jan 2019 23:07:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727034AbfA1XHK (ORCPT ); Mon, 28 Jan 2019 18:07:10 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:40333 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727006AbfA1XHJ (ORCPT ); Mon, 28 Jan 2019 18:07:09 -0500 Received: by mail-wm1-f66.google.com with SMTP id f188so15700476wmf.5 for ; Mon, 28 Jan 2019 15:07:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mathembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:in-reply-to:references; bh=P8mllz0KMgQrspybiLoEzeCMuG9uaqyD0z9whkWfzKE=; b=jfQRkV5F5Ir+c0YGbfb9M+4lA0QGZ3x4TGH4RqTPk4B/qoMD90ypdMBrpUwV6DVW2y 8JO1RRehTq14DYTr+ccmt/a8FkAFuBbiBZPEIKWzUzgj8ViYIIfu4WGd2Y8UdEIX7R3V rqH58zdcNdig0EdP1ZxcyXicnC8OEM5zRH1HJC+pzlLx7tD+2dsnIHSOaM2J6jD+8cQ5 v/zvvFzQHnztmQLgtf502ABatbqFpWsbiIV92pEDJ+zd+wGgq2w/6G4M8BGFUAuh2/Sb YQxusttllnBtIaYmfjwo2CzNzaVjgcE0ymGEEuBra0hngWIsdNWypqV02Whs6NRHj8w/ nhag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=P8mllz0KMgQrspybiLoEzeCMuG9uaqyD0z9whkWfzKE=; b=jRl2h1T3rc38foCRoFH8R9vykYOjSJQwjR4mT5bYSxd2MStHR35lRWiwrDFNLyvAhH MiofX4sFM+c3jJZCn5yonKBH6nPHpj7WnC862mNxRmyZwtF0g7A8SUMWFxhIPi+E9jdn XzcWF3xKSXG83UJfbEWn1+qTNGpf2bmzAknPIn7Dta8GBySz8LPcUPxJUMvtEcxf1n95 LkEYzew7UgdBbJUAPaHQvggi/6VoUr1AP238sr3Lm1JAn3j8FN1cI1No+DXYv8ScfPVX F/vVmV9axNmRKuId2pEnePe1SG0jLIlISBy0P3ZQm6DlQ+n1n4Fh9l5vxlE64ILZDw/2 oMsg== X-Gm-Message-State: AJcUukdyA8afBUbq9yVaXA32Y3YcznbsHXdv8A6xRygDxCPWKPZpWbkz o72TjD9y/udHOynbiq0LGNtgLyucqHy3hQ== X-Google-Smtp-Source: ALg8bN7OU88FhnN1JMqLpwgVf9WjztvYjOcowWC2tZUsYoqfxb/38abdDOFRJbaFi66+Kt3AYAyNgw== X-Received: by 2002:a1c:e910:: with SMTP id q16mr17617929wmc.68.1548716827685; Mon, 28 Jan 2019 15:07:07 -0800 (PST) Received: from diamond.mathembedded.com (host86-176-243-190.range86-176.btcentralplus.com. [86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.06 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:06 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 05/17] ARM: dts: exynos: Use bustop PLL as the source for MMC clocks on Exynos5260 Date: Mon, 28 Jan 2019 23:06:48 +0000 Message-Id: <20190128230700.7325-6-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP By default the MMC clock will be derived from mediatop PLL, which usually runs at 666MHz. However as most SD and MMC clocks are multiples or fractions of 100MHz, it makes more sense to use the bustop PLL which runs at 800MHz. Signed-off-by: Stuart Menefy --- arch/arm/boot/dts/exynos5260.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 55167850619c..14b423de9137 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -288,6 +288,14 @@ #size-cells = <0>; clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; clock-names = "biu", "ciu"; + assigned-clocks = + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>, + <&clock_top TOP_SCLK_MMC0>; + assigned-clock-parents = + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>; + assigned-clock-rates = <0>, <0>, <800000000>; fifo-depth = <64>; status = "disabled"; }; @@ -300,6 +308,14 @@ #size-cells = <0>; clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; clock-names = "biu", "ciu"; + assigned-clocks = + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>, + <&clock_top TOP_SCLK_MMC1>; + assigned-clock-parents = + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>; + assigned-clock-rates = <0>, <0>, <800000000>; fifo-depth = <64>; status = "disabled"; }; @@ -312,6 +328,14 @@ #size-cells = <0>; clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>; clock-names = "biu", "ciu"; + assigned-clocks = + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>, + <&clock_top TOP_SCLK_MMC2>; + assigned-clock-parents = + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>; + assigned-clock-rates = <0>, <0>, <800000000>; fifo-depth = <64>; status = "disabled"; };