| Message ID | 20190301122055.7135-19-a.hajda@samsung.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | drm/exynos: add support for GSCALER planes on Exynos5433 | expand |
On Fri, 1 Mar 2019 at 13:24, Andrzej Hajda <a.hajda@samsung.com> wrote: > > To support local paths both DECON and GSCALER should enable respective > Smart Deck clocks DSD and GSD. > > Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> > --- > arch/arm64/boot/dts/exynos/exynos5433.dtsi | 25 +++++++++++++--------- > 1 file changed, 15 insertions(+), 10 deletions(-) Hi Andrzej, You did not CC me on DTS patches. The DTS should go through arm-soc DT branch, not through drivers/subsystem. Any dependencies here and in next patch? Best regards, Krzysztof > > diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi > index e7cd3b67d818..e6d32b2fb3c0 100644 > --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi > @@ -848,12 +848,13 @@ > <&cmu_disp CLK_ACLK_XIU_DECON1X>, > <&cmu_disp CLK_PCLK_SMMU_DECON1X>, > <&cmu_disp CLK_SCLK_DECON_VCLK>, > - <&cmu_disp CLK_SCLK_DECON_ECLK>; > + <&cmu_disp CLK_SCLK_DECON_ECLK>, > + <&cmu_disp CLK_SCLK_DSD>; > clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", > "aclk_xiu_decon0x", "pclk_smmu_decon0x", > "aclk_smmu_decon1x", "aclk_xiu_decon1x", > "pclk_smmu_decon1x", "sclk_decon_vclk", > - "sclk_decon_eclk"; > + "sclk_decon_eclk", "dsd"; > power-domains = <&pd_disp>; > interrupt-names = "fifo", "vsync", "lcd_sys"; > interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, > @@ -890,12 +891,13 @@ > <&cmu_disp CLK_ACLK_XIU_TV1X>, > <&cmu_disp CLK_PCLK_SMMU_TV1X>, > <&cmu_disp CLK_SCLK_DECON_TV_VCLK>, > - <&cmu_disp CLK_SCLK_DECON_TV_ECLK>; > + <&cmu_disp CLK_SCLK_DECON_TV_ECLK>, > + <&cmu_disp CLK_SCLK_DSD>; > clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", > "aclk_xiu_decon0x", "pclk_smmu_decon0x", > "aclk_smmu_decon1x", "aclk_xiu_decon1x", > "pclk_smmu_decon1x", "sclk_decon_vclk", > - "sclk_decon_eclk"; > + "sclk_decon_eclk", "dsd"; > samsung,disp-sysreg = <&syscon_disp>; > power-domains = <&pd_disp>; > interrupt-names = "fifo", "vsync", "lcd_sys"; > @@ -1022,11 +1024,12 @@ > reg = <0x13c00000 0x1000>; > interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; > clock-names = "pclk", "aclk", "aclk_xiu", > - "aclk_gsclbend"; > + "aclk_gsclbend", "gsd"; > clocks = <&cmu_gscl CLK_PCLK_GSCL0>, > <&cmu_gscl CLK_ACLK_GSCL0>, > <&cmu_gscl CLK_ACLK_XIU_GSCLX>, > - <&cmu_gscl CLK_ACLK_GSCLBEND_333>; > + <&cmu_gscl CLK_ACLK_GSCLBEND_333>, > + <&cmu_gscl CLK_ACLK_GSD>; > iommus = <&sysmmu_gscl0>; > power-domains = <&pd_gscl>; > }; > @@ -1036,11 +1039,12 @@ > reg = <0x13c10000 0x1000>; > interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; > clock-names = "pclk", "aclk", "aclk_xiu", > - "aclk_gsclbend"; > + "aclk_gsclbend", "gsd"; > clocks = <&cmu_gscl CLK_PCLK_GSCL1>, > <&cmu_gscl CLK_ACLK_GSCL1>, > <&cmu_gscl CLK_ACLK_XIU_GSCLX>, > - <&cmu_gscl CLK_ACLK_GSCLBEND_333>; > + <&cmu_gscl CLK_ACLK_GSCLBEND_333>, > + <&cmu_gscl CLK_ACLK_GSD>; > iommus = <&sysmmu_gscl1>; > power-domains = <&pd_gscl>; > }; > @@ -1050,11 +1054,12 @@ > reg = <0x13c20000 0x1000>; > interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; > clock-names = "pclk", "aclk", "aclk_xiu", > - "aclk_gsclbend"; > + "aclk_gsclbend", "gsd"; > clocks = <&cmu_gscl CLK_PCLK_GSCL2>, > <&cmu_gscl CLK_ACLK_GSCL2>, > <&cmu_gscl CLK_ACLK_XIU_GSCLX>, > - <&cmu_gscl CLK_ACLK_GSCLBEND_333>; > + <&cmu_gscl CLK_ACLK_GSCLBEND_333>, > + <&cmu_gscl CLK_ACLK_GSD>; > iommus = <&sysmmu_gscl2>; > power-domains = <&pd_gscl>; > }; > -- > 2.17.1 >
On 05.03.2019 10:28, Krzysztof Kozlowski wrote: > On Fri, 1 Mar 2019 at 13:24, Andrzej Hajda <a.hajda@samsung.com> wrote: >> To support local paths both DECON and GSCALER should enable respective >> Smart Deck clocks DSD and GSD. >> >> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> >> --- >> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 25 +++++++++++++--------- >> 1 file changed, 15 insertions(+), 10 deletions(-) > Hi Andrzej, > > You did not CC me on DTS patches. The DTS should go through arm-soc DT > branch, not through drivers/subsystem. > > Any dependencies here and in next patch? Ups, forgive me my distraction. DTS patches should be applied before following driver changes. Regards Andrzej > > Best regards, > Krzysztof > >> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi >> index e7cd3b67d818..e6d32b2fb3c0 100644 >> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi >> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi >> @@ -848,12 +848,13 @@ >> <&cmu_disp CLK_ACLK_XIU_DECON1X>, >> <&cmu_disp CLK_PCLK_SMMU_DECON1X>, >> <&cmu_disp CLK_SCLK_DECON_VCLK>, >> - <&cmu_disp CLK_SCLK_DECON_ECLK>; >> + <&cmu_disp CLK_SCLK_DECON_ECLK>, >> + <&cmu_disp CLK_SCLK_DSD>; >> clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", >> "aclk_xiu_decon0x", "pclk_smmu_decon0x", >> "aclk_smmu_decon1x", "aclk_xiu_decon1x", >> "pclk_smmu_decon1x", "sclk_decon_vclk", >> - "sclk_decon_eclk"; >> + "sclk_decon_eclk", "dsd"; >> power-domains = <&pd_disp>; >> interrupt-names = "fifo", "vsync", "lcd_sys"; >> interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, >> @@ -890,12 +891,13 @@ >> <&cmu_disp CLK_ACLK_XIU_TV1X>, >> <&cmu_disp CLK_PCLK_SMMU_TV1X>, >> <&cmu_disp CLK_SCLK_DECON_TV_VCLK>, >> - <&cmu_disp CLK_SCLK_DECON_TV_ECLK>; >> + <&cmu_disp CLK_SCLK_DECON_TV_ECLK>, >> + <&cmu_disp CLK_SCLK_DSD>; >> clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", >> "aclk_xiu_decon0x", "pclk_smmu_decon0x", >> "aclk_smmu_decon1x", "aclk_xiu_decon1x", >> "pclk_smmu_decon1x", "sclk_decon_vclk", >> - "sclk_decon_eclk"; >> + "sclk_decon_eclk", "dsd"; >> samsung,disp-sysreg = <&syscon_disp>; >> power-domains = <&pd_disp>; >> interrupt-names = "fifo", "vsync", "lcd_sys"; >> @@ -1022,11 +1024,12 @@ >> reg = <0x13c00000 0x1000>; >> interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; >> clock-names = "pclk", "aclk", "aclk_xiu", >> - "aclk_gsclbend"; >> + "aclk_gsclbend", "gsd"; >> clocks = <&cmu_gscl CLK_PCLK_GSCL0>, >> <&cmu_gscl CLK_ACLK_GSCL0>, >> <&cmu_gscl CLK_ACLK_XIU_GSCLX>, >> - <&cmu_gscl CLK_ACLK_GSCLBEND_333>; >> + <&cmu_gscl CLK_ACLK_GSCLBEND_333>, >> + <&cmu_gscl CLK_ACLK_GSD>; >> iommus = <&sysmmu_gscl0>; >> power-domains = <&pd_gscl>; >> }; >> @@ -1036,11 +1039,12 @@ >> reg = <0x13c10000 0x1000>; >> interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; >> clock-names = "pclk", "aclk", "aclk_xiu", >> - "aclk_gsclbend"; >> + "aclk_gsclbend", "gsd"; >> clocks = <&cmu_gscl CLK_PCLK_GSCL1>, >> <&cmu_gscl CLK_ACLK_GSCL1>, >> <&cmu_gscl CLK_ACLK_XIU_GSCLX>, >> - <&cmu_gscl CLK_ACLK_GSCLBEND_333>; >> + <&cmu_gscl CLK_ACLK_GSCLBEND_333>, >> + <&cmu_gscl CLK_ACLK_GSD>; >> iommus = <&sysmmu_gscl1>; >> power-domains = <&pd_gscl>; >> }; >> @@ -1050,11 +1054,12 @@ >> reg = <0x13c20000 0x1000>; >> interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; >> clock-names = "pclk", "aclk", "aclk_xiu", >> - "aclk_gsclbend"; >> + "aclk_gsclbend", "gsd"; >> clocks = <&cmu_gscl CLK_PCLK_GSCL2>, >> <&cmu_gscl CLK_ACLK_GSCL2>, >> <&cmu_gscl CLK_ACLK_XIU_GSCLX>, >> - <&cmu_gscl CLK_ACLK_GSCLBEND_333>; >> + <&cmu_gscl CLK_ACLK_GSCLBEND_333>, >> + <&cmu_gscl CLK_ACLK_GSD>; >> iommus = <&sysmmu_gscl2>; >> power-domains = <&pd_gscl>; >> }; >> -- >> 2.17.1 >> >
On Tue, 5 Mar 2019 at 10:36, Andrzej Hajda <a.hajda@samsung.com> wrote: > > On 05.03.2019 10:28, Krzysztof Kozlowski wrote: > > On Fri, 1 Mar 2019 at 13:24, Andrzej Hajda <a.hajda@samsung.com> wrote: > >> To support local paths both DECON and GSCALER should enable respective > >> Smart Deck clocks DSD and GSD. > >> > >> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> > >> --- > >> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 25 +++++++++++++--------- > >> 1 file changed, 15 insertions(+), 10 deletions(-) > > Hi Andrzej, > > > > You did not CC me on DTS patches. The DTS should go through arm-soc DT > > branch, not through drivers/subsystem. > > > > Any dependencies here and in next patch? > > > Ups, forgive me my distraction. DTS patches should be applied before > following driver changes. I can take them after merge window and either prepare a separate branch+tag or the following driver changes will wait till next release. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index e7cd3b67d818..e6d32b2fb3c0 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -848,12 +848,13 @@ <&cmu_disp CLK_ACLK_XIU_DECON1X>, <&cmu_disp CLK_PCLK_SMMU_DECON1X>, <&cmu_disp CLK_SCLK_DECON_VCLK>, - <&cmu_disp CLK_SCLK_DECON_ECLK>; + <&cmu_disp CLK_SCLK_DECON_ECLK>, + <&cmu_disp CLK_SCLK_DSD>; clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x", "pclk_smmu_decon0x", "aclk_smmu_decon1x", "aclk_xiu_decon1x", "pclk_smmu_decon1x", "sclk_decon_vclk", - "sclk_decon_eclk"; + "sclk_decon_eclk", "dsd"; power-domains = <&pd_disp>; interrupt-names = "fifo", "vsync", "lcd_sys"; interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, @@ -890,12 +891,13 @@ <&cmu_disp CLK_ACLK_XIU_TV1X>, <&cmu_disp CLK_PCLK_SMMU_TV1X>, <&cmu_disp CLK_SCLK_DECON_TV_VCLK>, - <&cmu_disp CLK_SCLK_DECON_TV_ECLK>; + <&cmu_disp CLK_SCLK_DECON_TV_ECLK>, + <&cmu_disp CLK_SCLK_DSD>; clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x", "pclk_smmu_decon0x", "aclk_smmu_decon1x", "aclk_xiu_decon1x", "pclk_smmu_decon1x", "sclk_decon_vclk", - "sclk_decon_eclk"; + "sclk_decon_eclk", "dsd"; samsung,disp-sysreg = <&syscon_disp>; power-domains = <&pd_disp>; interrupt-names = "fifo", "vsync", "lcd_sys"; @@ -1022,11 +1024,12 @@ reg = <0x13c00000 0x1000>; interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; clock-names = "pclk", "aclk", "aclk_xiu", - "aclk_gsclbend"; + "aclk_gsclbend", "gsd"; clocks = <&cmu_gscl CLK_PCLK_GSCL0>, <&cmu_gscl CLK_ACLK_GSCL0>, <&cmu_gscl CLK_ACLK_XIU_GSCLX>, - <&cmu_gscl CLK_ACLK_GSCLBEND_333>; + <&cmu_gscl CLK_ACLK_GSCLBEND_333>, + <&cmu_gscl CLK_ACLK_GSD>; iommus = <&sysmmu_gscl0>; power-domains = <&pd_gscl>; }; @@ -1036,11 +1039,12 @@ reg = <0x13c10000 0x1000>; interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; clock-names = "pclk", "aclk", "aclk_xiu", - "aclk_gsclbend"; + "aclk_gsclbend", "gsd"; clocks = <&cmu_gscl CLK_PCLK_GSCL1>, <&cmu_gscl CLK_ACLK_GSCL1>, <&cmu_gscl CLK_ACLK_XIU_GSCLX>, - <&cmu_gscl CLK_ACLK_GSCLBEND_333>; + <&cmu_gscl CLK_ACLK_GSCLBEND_333>, + <&cmu_gscl CLK_ACLK_GSD>; iommus = <&sysmmu_gscl1>; power-domains = <&pd_gscl>; }; @@ -1050,11 +1054,12 @@ reg = <0x13c20000 0x1000>; interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; clock-names = "pclk", "aclk", "aclk_xiu", - "aclk_gsclbend"; + "aclk_gsclbend", "gsd"; clocks = <&cmu_gscl CLK_PCLK_GSCL2>, <&cmu_gscl CLK_ACLK_GSCL2>, <&cmu_gscl CLK_ACLK_XIU_GSCLX>, - <&cmu_gscl CLK_ACLK_GSCLBEND_333>; + <&cmu_gscl CLK_ACLK_GSCLBEND_333>, + <&cmu_gscl CLK_ACLK_GSD>; iommus = <&sysmmu_gscl2>; power-domains = <&pd_gscl>; };
To support local paths both DECON and GSCALER should enable respective Smart Deck clocks DSD and GSD. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 25 +++++++++++++--------- 1 file changed, 15 insertions(+), 10 deletions(-)