From patchwork Mon Mar 25 07:13:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 10868021 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4740D14DE for ; Mon, 25 Mar 2019 07:14:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2CB222924B for ; Mon, 25 Mar 2019 07:14:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 210012924E; Mon, 25 Mar 2019 07:14:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 103F12924F for ; Mon, 25 Mar 2019 07:13:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729789AbfCYHN6 (ORCPT ); Mon, 25 Mar 2019 03:13:58 -0400 Received: from mailout1.w1.samsung.com ([210.118.77.11]:41917 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729764AbfCYHN6 (ORCPT ); Mon, 25 Mar 2019 03:13:58 -0400 Received: from eucas1p2.samsung.com (unknown [182.198.249.207]) by mailout1.w1.samsung.com (KnoxPortal) with ESMTP id 20190325071356euoutp01bf9b9096e228ff5bb8e4a90acf81aed1~PIjvOHQVy0752607526euoutp01L; Mon, 25 Mar 2019 07:13:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.w1.samsung.com 20190325071356euoutp01bf9b9096e228ff5bb8e4a90acf81aed1~PIjvOHQVy0752607526euoutp01L DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1553498036; bh=ONtOvg0HOepEZFkPO7He4sHTIxdEid424A9z53T9Abw=; h=From:To:Cc:Subject:Date:In-reply-to:References:From; b=SHqnOBfS+uhWgsnprdnsn05q7CBchuwGsZoj4pz8XENhUFX7uWIS7WcxUgW3IyxlI XJnTlpl3PXInmiGmgMpDuHBBlD0jQmZD87jEY+32gl/zs89ZijD7AYSB0kLvESriHK eUvPwJk5oYTBOBeQHANjUhFQS3d/1iyyK50V2hsw= Received: from eusmges1new.samsung.com (unknown [203.254.199.242]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20190325071356eucas1p19591f333e08a3c0304c1be191d364fd2~PIjuzQqa83105231052eucas1p1m; Mon, 25 Mar 2019 07:13:56 +0000 (GMT) Received: from eucas1p1.samsung.com ( [182.198.249.206]) by eusmges1new.samsung.com (EUCPMTA) with SMTP id 7E.5E.04298.3BF789C5; Mon, 25 Mar 2019 07:13:55 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20190325071355eucas1p1bc10232953b0d9f122ee7d3d532374e8~PIjt_kJsl2364523645eucas1p1G; Mon, 25 Mar 2019 07:13:55 +0000 (GMT) X-AuditID: cbfec7f2-f2dff700000010ca-b2-5c987fb3079d Received: from eusync3.samsung.com ( [203.254.199.213]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id B1.69.04146.3BF789C5; Mon, 25 Mar 2019 07:13:55 +0000 (GMT) Received: from AMDC3748.DIGITAL.local ([106.120.51.74]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0POW003QHUR43P00@eusync3.samsung.com>; Mon, 25 Mar 2019 07:13:55 +0000 (GMT) From: Andrzej Hajda To: Inki Dae Cc: Andrzej Hajda , Bartlomiej Zolnierkiewicz , Marek Szyprowski , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 RESEND 05/24] drm/exynos: drop exynos_drm_plane_config structure Date: Mon, 25 Mar 2019 08:13:30 +0100 Message-id: <20190325071349.22600-6-a.hajda@samsung.com> X-Mailer: git-send-email 2.17.1 In-reply-to: <20190325071349.22600-1-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprBIsWRmVeSWpSXmKPExsWy7djPc7qb62fEGGz+ZWlxa905VouNM9az Wlz5+p7NYtL9CSwW589vYLeYcX4fk8XaI3fZHdg9Nq3qZPO4332cyaNvyypGj8+b5AJYorhs UlJzMstSi/TtErgylre3sRZMbWWsWH55NXsD47K8LkZODgkBE4k5E8+zgNhCAisYJe5N54aw PzNKPH0p1cXIAVazZQ9QCRdQeBmjxPKZ3YwQzn9GiUuTrzCDNLAJaEr83XyTDcQWEVCWWLWv nR2kiFngN6PE9OXb2EESwgKhEvPezAGzWQRUJX70/2IFsXkFLCQm7NzEDHGRvMTqDQfAbE4B S4n/py8xgwySEGhkk/iw/ApUkYvElDXNULaMRGfHQSYIu17i/ooWqIYORomtG3ZCFVlLHD5+ EWwbswCfxKRt05khfuOV6GgTgijxkHh85gnUnz2MEnP+rGSewCixgJFhFaN4amlxbnpqsWFe arlecWJucWleul5yfu4mRmB8nf53/NMOxq+Xkg4xCnAwKvHwvtg5PUaINbGsuDL3EKMEB7OS CO8T0RkxQrwpiZVVqUX58UWlOanFhxilOViUxHmrGR5ECwmkJ5akZqemFqQWwWSZODilGhjT fUPd5Y7dkRe2mf7JpeNF+LQpTQJFj9zvlv1idvWJF1N5253PHTKt+LT4LsPNen5FimX762ct +nc7UHuPM/f6mS8Ftj7LWVukrvCxhV+nnHFZ2y1Jvt0bHCLEwpctnLGmd7tbqlHPR7uosLbC xJQ190MFswJ/TObh5Sj8+3ETW166a2DhfiWW4oxEQy3mouJEABHl2W+rAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpmluLIzCtJLcpLzFFi42I5/e/4Vd3N9TNiDB6dFLG4te4cq8XGGetZ La58fc9mMen+BBaL8+c3sFvMOL+PyWLtkbvsDuwem1Z1snnc7z7O5NG3ZRWjx+dNcgEsUVw2 Kak5mWWpRfp2CVwZy9vbWAumtjJWLL+8mr2BcVleFyMHh4SAicSWPSxdjFwcQgJLGCXe3nnK CuE0MknMXLeesYuRk4NNQFPi7+abbCC2iICyxKp97ewgRcwCvxklPs/4ygySEBYIlZj3Zg47 iM0ioCrxo/8XK4jNK2AhMWHnJrAaCQF5idUbDoDZnAKWEv9PXwKzhYBq9i5rZJ/AyLOAkWEV o0hqaXFuem6xoV5xYm5xaV66XnJ+7iZGYNBsO/Zz8w7GSxuDDzEKcDAq8fA67JkeI8SaWFZc mXuIUYKDWUmE94nojBgh3pTEyqrUovz4otKc1OJDjNIcLErivOcNKqOEBNITS1KzU1MLUotg skwcnFINjLxTlKQk3zrYFD7+u+/58j/9f8VO+EV+b5xYsUjdTa7ErvL+tOTfpx+s8TDdwvZ5 wuyCTWqrhYXOd/VVVUTP+fe9cotzRWKY2OGFO+Il/BZ7LrepTZOK+W7rk6im9nHxkxAm6+fH 1R+7+Z7S/qYd1zztgfLcKSZV37ynmjOrn7Nnfi3zNe/CYyWW4oxEQy3mouJEAGCwBq0WAgAA X-CMS-MailID: 20190325071355eucas1p1bc10232953b0d9f122ee7d3d532374e8 CMS-TYPE: 201P X-CMS-RootMailID: 20190325071355eucas1p1bc10232953b0d9f122ee7d3d532374e8 References: <20190325071349.22600-1-a.hajda@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP exynos_drm_plane_config must be present for every plane, and most fields are redundant with exynos_drm_plane: - pixel_formats, num_pixel_formats are stored in plane.base.format_*, - type is stored in plane.base.type, - zpos is always equal to plane.index. The only non-redundant field capabilities can be moved to exynos_drm_plane. As consequence of removing the structure some code should be refactored. The patch should not have functional changes. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 18 +++--- drivers/gpu/drm/exynos/exynos7_drm_decon.c | 11 +--- drivers/gpu/drm/exynos/exynos_drm_drv.h | 39 ++++--------- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 17 ++---- drivers/gpu/drm/exynos/exynos_drm_plane.c | 56 +++++++++--------- drivers/gpu/drm/exynos/exynos_drm_vidi.c | 11 +--- drivers/gpu/drm/exynos/exynos_mixer.c | 58 +++++++------------ 7 files changed, 76 insertions(+), 134 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index 24df0b307b2f..ae0f475eb633 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -56,7 +56,6 @@ struct decon_context { struct drm_device *drm_dev; struct exynos_drm_crtc *crtc; struct exynos_drm_plane planes[WINDOWS_NR]; - struct exynos_drm_plane_config configs[WINDOWS_NR]; void __iomem *addr; struct regmap *sysreg; struct clk *clks[ARRAY_SIZE(decon_clks_name)]; @@ -608,22 +607,19 @@ static int decon_bind(struct device *dev, struct device *master, void *data) struct drm_device *drm_dev = data; struct exynos_drm_plane *exynos_plane; enum exynos_drm_output_type out_type; - unsigned int win; + unsigned int i; int ret; ctx->drm_dev = drm_dev; - for (win = ctx->first_win; win < WINDOWS_NR; win++) { - ctx->configs[win].pixel_formats = decon_formats; - ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); - ctx->configs[win].zpos = win - ctx->first_win; - ctx->configs[win].type = decon_win_types[win]; - ctx->configs[win].capabilities = EXYNOS_DRM_PLANE_CAP_ZPOS + for (i = ctx->first_win; i < WINDOWS_NR; i++) { + ctx->planes[i].index = i - ctx->first_win; + ctx->planes[i].capabilities = EXYNOS_DRM_PLANE_CAP_ZPOS | EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND; - - ret = exynos_plane_init(drm_dev, &ctx->planes[win], win, - &ctx->configs[win]); + ret = exynos_plane_init(drm_dev, &ctx->planes[i], + decon_formats, ARRAY_SIZE(decon_formats), + decon_win_types[i]); if (ret) return ret; } diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index 812941b84287..6d462f057531 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -44,7 +44,6 @@ struct decon_context { struct drm_device *drm_dev; struct exynos_drm_crtc *crtc; struct exynos_drm_plane planes[WINDOWS_NR]; - struct exynos_drm_plane_config configs[WINDOWS_NR]; struct clk *pclk; struct clk *aclk; struct clk *eclk; @@ -626,13 +625,9 @@ static int decon_bind(struct device *dev, struct device *master, void *data) } for (i = 0; i < WINDOWS_NR; i++) { - ctx->configs[i].pixel_formats = decon_formats; - ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats); - ctx->configs[i].zpos = i; - ctx->configs[i].type = decon_win_types[i]; - - ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, - &ctx->configs[i]); + ctx->planes[i].index = i; + ret = exynos_plane_init(drm_dev, &ctx->planes[i], decon_formats, + ARRAY_SIZE(decon_formats), decon_win_types[i]); if (ret) return ret; } diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index 1f6bb5516170..1d4ef0245958 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -71,11 +71,19 @@ to_exynos_plane_state(struct drm_plane_state *state) return container_of(state, struct exynos_drm_plane_state, base); } +#define EXYNOS_DRM_PLANE_CAP_DOUBLE (1 << 0) +#define EXYNOS_DRM_PLANE_CAP_SCALE (1 << 1) +#define EXYNOS_DRM_PLANE_CAP_ZPOS (1 << 2) +#define EXYNOS_DRM_PLANE_CAP_TILE (1 << 3) +#define EXYNOS_DRM_PLANE_CAP_PIX_BLEND (1 << 4) +#define EXYNOS_DRM_PLANE_CAP_WIN_BLEND (1 << 5) + /* * Exynos drm common overlay structure. * * @base: plane object * @index: hardware index of the overlay layer + * @capabilities: supported features (see EXYNOS_DRM_PLANE_CAP_*) * * this structure is common to exynos SoC and its contents would be copied * to hardware specific overlay info. @@ -83,38 +91,13 @@ to_exynos_plane_state(struct drm_plane_state *state) struct exynos_drm_plane { struct drm_plane base; - const struct exynos_drm_plane_config *config; unsigned int index; -}; - -#define EXYNOS_DRM_PLANE_CAP_DOUBLE (1 << 0) -#define EXYNOS_DRM_PLANE_CAP_SCALE (1 << 1) -#define EXYNOS_DRM_PLANE_CAP_ZPOS (1 << 2) -#define EXYNOS_DRM_PLANE_CAP_TILE (1 << 3) -#define EXYNOS_DRM_PLANE_CAP_PIX_BLEND (1 << 4) -#define EXYNOS_DRM_PLANE_CAP_WIN_BLEND (1 << 5) - -/* - * Exynos DRM plane configuration structure. - * - * @zpos: initial z-position of the plane. - * @type: type of the plane (primary, cursor or overlay). - * @pixel_formats: supported pixel formats. - * @num_pixel_formats: number of elements in 'pixel_formats'. - * @capabilities: supported features (see EXYNOS_DRM_PLANE_CAP_*) - */ - -struct exynos_drm_plane_config { - unsigned int zpos; - enum drm_plane_type type; - const uint32_t *pixel_formats; - unsigned int num_pixel_formats; unsigned int capabilities; }; -int exynos_plane_init(struct drm_device *dev, - struct exynos_drm_plane *exynos_plane, unsigned int index, - const struct exynos_drm_plane_config *config); +int exynos_plane_init(struct drm_device *dev, struct exynos_drm_plane *plane, + const uint32_t *pixel_formats, int num_pixel_formats, + enum drm_plane_type type); /* * Exynos drm crtc ops diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index b1a9502a4140..2d34ca375ee1 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -171,7 +171,6 @@ struct fimd_context { struct drm_device *drm_dev; struct exynos_drm_crtc *crtc; struct exynos_drm_plane planes[WINDOWS_NR]; - struct exynos_drm_plane_config configs[WINDOWS_NR]; struct clk *bus_clk; struct clk *lcd_clk; void __iomem *regs; @@ -1044,16 +1043,12 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) ctx->drm_dev = drm_dev; for (i = 0; i < WINDOWS_NR; i++) { - ctx->configs[i].pixel_formats = fimd_formats; - ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); - ctx->configs[i].zpos = i; - ctx->configs[i].type = fimd_win_types[i]; - ctx->configs[i].capabilities = EXYNOS_DRM_PLANE_CAP_ZPOS - | EXYNOS_DRM_PLANE_CAP_WIN_BLEND - | EXYNOS_DRM_PLANE_CAP_PIX_BLEND; - - ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, - &ctx->configs[i]); + ctx->planes[i].index = i; + ctx->planes[i].capabilities = EXYNOS_DRM_PLANE_CAP_ZPOS + | EXYNOS_DRM_PLANE_CAP_WIN_BLEND + | EXYNOS_DRM_PLANE_CAP_PIX_BLEND; + ret = exynos_plane_init(drm_dev, &ctx->planes[i], fimd_formats, + ARRAY_SIZE(fimd_formats), fimd_win_types[i]); if (ret) return ret; } diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index 8af0eba3f362..e1aa504539fa 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -138,7 +138,7 @@ static void exynos_drm_plane_reset(struct drm_plane *plane) exynos_state = kzalloc(sizeof(*exynos_state), GFP_KERNEL); if (exynos_state) { __drm_atomic_helper_plane_reset(plane, &exynos_state->base); - plane->state->zpos = exynos_plane->config->zpos; + plane->state->zpos = exynos_plane->index; } } @@ -176,14 +176,14 @@ static struct drm_plane_funcs exynos_plane_funcs = { }; static int -exynos_drm_plane_check_format(const struct exynos_drm_plane_config *config, - struct exynos_drm_plane_state *state) +exynos_drm_plane_check_format(struct exynos_drm_plane_state *state) { + struct exynos_drm_plane *plane = to_exynos_plane(state->base.plane); struct drm_framebuffer *fb = state->base.fb; switch (fb->modifier) { case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE: - if (!(config->capabilities & EXYNOS_DRM_PLANE_CAP_TILE)) + if (!(plane->capabilities & EXYNOS_DRM_PLANE_CAP_TILE)) return -ENOTSUPP; break; @@ -199,12 +199,12 @@ exynos_drm_plane_check_format(const struct exynos_drm_plane_config *config, } static int -exynos_drm_plane_check_size(const struct exynos_drm_plane_config *config, - struct exynos_drm_plane_state *state) +exynos_drm_plane_check_size(struct exynos_drm_plane_state *state) { + struct exynos_drm_plane *plane = to_exynos_plane(state->base.plane); bool width_ok = false, height_ok = false; - if (config->capabilities & EXYNOS_DRM_PLANE_CAP_SCALE) + if (plane->capabilities & EXYNOS_DRM_PLANE_CAP_SCALE) return 0; if (state->src.w == state->crtc.w) @@ -213,11 +213,11 @@ exynos_drm_plane_check_size(const struct exynos_drm_plane_config *config, if (state->src.h == state->crtc.h) height_ok = true; - if ((config->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) && + if ((plane->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) && state->h_ratio == (1 << 15)) width_ok = true; - if ((config->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) && + if ((plane->capabilities & EXYNOS_DRM_PLANE_CAP_DOUBLE) && state->v_ratio == (1 << 15)) height_ok = true; @@ -231,7 +231,6 @@ exynos_drm_plane_check_size(const struct exynos_drm_plane_config *config, static int exynos_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { - struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane); struct exynos_drm_plane_state *exynos_state = to_exynos_plane_state(state); int ret = 0; @@ -242,11 +241,11 @@ static int exynos_plane_atomic_check(struct drm_plane *plane, /* translate state into exynos_state */ exynos_plane_mode_set(exynos_state); - ret = exynos_drm_plane_check_format(exynos_plane->config, exynos_state); + ret = exynos_drm_plane_check_format(exynos_state); if (ret) return ret; - ret = exynos_drm_plane_check_size(exynos_plane->config, exynos_state); + ret = exynos_drm_plane_check_size(exynos_state); return ret; } @@ -292,40 +291,37 @@ static void exynos_plane_attach_zpos_property(struct drm_plane *plane, drm_plane_create_zpos_property(plane, zpos, 0, MAX_PLANE - 1); } -int exynos_plane_init(struct drm_device *dev, - struct exynos_drm_plane *exynos_plane, unsigned int index, - const struct exynos_drm_plane_config *config) +int exynos_plane_init(struct drm_device *dev, struct exynos_drm_plane *plane, + const uint32_t *pixel_formats, int num_pixel_formats, + enum drm_plane_type type) { int err; unsigned int supported_modes = BIT(DRM_MODE_BLEND_PIXEL_NONE) | BIT(DRM_MODE_BLEND_PREMULTI) | BIT(DRM_MODE_BLEND_COVERAGE); - struct drm_plane *plane = &exynos_plane->base; + struct drm_plane *bplane = &plane->base; - err = drm_universal_plane_init(dev, &exynos_plane->base, + err = drm_universal_plane_init(dev, bplane, 1 << dev->mode_config.num_crtc, &exynos_plane_funcs, - config->pixel_formats, - config->num_pixel_formats, - NULL, config->type, NULL); + pixel_formats, + num_pixel_formats, + NULL, type, NULL); if (err) { DRM_ERROR("failed to initialize plane\n"); return err; } - drm_plane_helper_add(&exynos_plane->base, &plane_helper_funcs); - - exynos_plane->index = index; - exynos_plane->config = config; + drm_plane_helper_add(bplane, &plane_helper_funcs); - exynos_plane_attach_zpos_property(&exynos_plane->base, config->zpos, - !(config->capabilities & EXYNOS_DRM_PLANE_CAP_ZPOS)); + exynos_plane_attach_zpos_property(bplane, plane->index, + !(plane->capabilities & EXYNOS_DRM_PLANE_CAP_ZPOS)); - if (config->capabilities & EXYNOS_DRM_PLANE_CAP_PIX_BLEND) - drm_plane_create_blend_mode_property(plane, supported_modes); + if (plane->capabilities & EXYNOS_DRM_PLANE_CAP_PIX_BLEND) + drm_plane_create_blend_mode_property(bplane, supported_modes); - if (config->capabilities & EXYNOS_DRM_PLANE_CAP_WIN_BLEND) - drm_plane_create_alpha_property(plane); + if (plane->capabilities & EXYNOS_DRM_PLANE_CAP_WIN_BLEND) + drm_plane_create_alpha_property(bplane); return 0; } diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c index ec30d5aca9aa..b61ae3415b8c 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c @@ -378,21 +378,14 @@ static int vidi_bind(struct device *dev, struct device *master, void *data) struct drm_device *drm_dev = data; struct drm_encoder *encoder = &ctx->encoder; struct exynos_drm_plane *exynos_plane; - struct exynos_drm_plane_config plane_config = { 0 }; unsigned int i; int ret; ctx->drm_dev = drm_dev; - plane_config.pixel_formats = formats; - plane_config.num_pixel_formats = ARRAY_SIZE(formats); - for (i = 0; i < WINDOWS_NR; i++) { - plane_config.zpos = i; - plane_config.type = vidi_win_types[i]; - - ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, - &plane_config); + ret = exynos_plane_init(drm_dev, &ctx->planes[i], formats, + ARRAY_SIZE(formats), vidi_win_types[i]); if (ret) return ret; } diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index ef50943cc9eb..1c82265acf0a 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -123,37 +123,6 @@ struct mixer_drv_data { bool has_sclk; }; -static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = { - { - .zpos = 0, - .type = DRM_PLANE_TYPE_PRIMARY, - .pixel_formats = mixer_formats, - .num_pixel_formats = ARRAY_SIZE(mixer_formats), - .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE | - EXYNOS_DRM_PLANE_CAP_ZPOS | - EXYNOS_DRM_PLANE_CAP_PIX_BLEND | - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - }, { - .zpos = 1, - .type = DRM_PLANE_TYPE_CURSOR, - .pixel_formats = mixer_formats, - .num_pixel_formats = ARRAY_SIZE(mixer_formats), - .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE | - EXYNOS_DRM_PLANE_CAP_ZPOS | - EXYNOS_DRM_PLANE_CAP_PIX_BLEND | - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - }, { - .zpos = 2, - .type = DRM_PLANE_TYPE_OVERLAY, - .pixel_formats = vp_formats, - .num_pixel_formats = ARRAY_SIZE(vp_formats), - .capabilities = EXYNOS_DRM_PLANE_CAP_SCALE | - EXYNOS_DRM_PLANE_CAP_ZPOS | - EXYNOS_DRM_PLANE_CAP_TILE | - EXYNOS_DRM_PLANE_CAP_WIN_BLEND, - }, -}; - static const u8 filter_y_horiz_tap8[] = { 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 0, 0, 0, @@ -1173,18 +1142,33 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data) struct exynos_drm_plane *exynos_plane; unsigned int i; int ret; + static enum drm_plane_type types[] = { DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_CURSOR, DRM_PLANE_TYPE_OVERLAY }; ret = mixer_initialize(ctx, drm_dev); if (ret) return ret; - for (i = 0; i < MIXER_WIN_NR; i++) { - if (i == VP_DEFAULT_WIN && !test_bit(MXR_BIT_VP_ENABLED, - &ctx->flags)) - continue; + for (i = 0; i < VP_DEFAULT_WIN; i++) { + ctx->planes[i].index = i; + ctx->planes[i].capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE | + EXYNOS_DRM_PLANE_CAP_ZPOS | + EXYNOS_DRM_PLANE_CAP_PIX_BLEND | + EXYNOS_DRM_PLANE_CAP_WIN_BLEND; + ret = exynos_plane_init(drm_dev, &ctx->planes[i], mixer_formats, + ARRAY_SIZE(mixer_formats), types[i]); + if (ret) + return ret; + } - ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, - &plane_configs[i]); + if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) { + ctx->planes[i].index = i; + ctx->planes[i].capabilities = EXYNOS_DRM_PLANE_CAP_SCALE | + EXYNOS_DRM_PLANE_CAP_ZPOS | + EXYNOS_DRM_PLANE_CAP_TILE | + EXYNOS_DRM_PLANE_CAP_WIN_BLEND; + ret = exynos_plane_init(drm_dev, &ctx->planes[i], vp_formats, + ARRAY_SIZE(vp_formats), types[i]); if (ret) return ret; }