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Mon, 15 Jul 2019 12:44:40 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, a.hajda@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba Subject: [PATCH v1 10/50] clk: samsung: change ACLK100_NOC clocks definitions Exynos5x Date: Mon, 15 Jul 2019 14:43:37 +0200 Message-Id: <20190715124417.4787-11-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrDKsWRmVeSWpSXmKPExsWy7djP87pWpTqxBldmqFjcWneO1WLjjPWs Fte/PGe1mH8EyO1//JrZ4vz5DewWZ5vesFvcapCx2PT4GqvFx557rBaXd81hs5hxfh+Txdoj d9ktll6/yGRx8ZSrxe3GFWwWrXuPsFscftPOavHv2kYWB2GPNfPWMHq8v9HK7rFpVSebx+Yl 9R4H3+1h8ujbsorR4/MmuQD2KC6blNSczLLUIn27BK6Mc8tOMhdckqiY/uYLSwNjv2gXIweH hICJxMEVGV2MXBxCAisYJfo+/mODcL4wSrQ0TWWHcD4zSqw9eJK1i5ETrGPOrJUsEInljBJd 8/+wwrWcf/+JGWQum4CexI5VhSANIgJLGCWO/EwCqWEWuMkksefJTrBJwgIREvM/72QGsVkE VCWu/mhiArF5Bewlds7YzgSxTV5i9YYDYDWcQPGf0y6A3SchcIld4vvZZSwQRS4SUy/0MELY whKvjm9hh7BlJE5P7oGqKZZo6F0IVVMj8bh/LlSNtcTh4xdZQY5mFtCUWL9LHxIujhKfLgRD mHwSN94KghQzA5mTtk1nhgjzSnS0CUHM0JDY0nMB6mAxieVrpkHN9pC427oeGoaTGCVeXpvO MoFRfhbCrgWMjKsYxVNLi3PTU4uN8lLL9YoTc4tL89L1kvNzNzEC09Tpf8e/7GDc9SfpEKMA B6MSD69DinasEGtiWXFl7iFGCQ5mJRFe269AId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rzVDA+i hQTSE0tSs1NTC1KLYLJMHJxSDYyBPLn/buzlsONfYM+wWuMH/5vP4jdl10wyfMzykydoypHk gHUaaSYvxdbcLpHgW55VFdphf+ju+Tk2ZodS5+XxCqq6nMmc9zp45dGcb/eXhJ4/VctsoXrI rOdl8x45gbV/J/7+le8T89vBe2Lvp5o5PFXfDhRNjOPNPB4QwL1LSePJxI/vcpqVWIozEg21 mIuKEwG5y7KbTwMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAIsWRmVeSWpSXmKPExsVy+t/xe7qWpTqxBr++qVncWneO1WLjjPWs Fte/PGe1mH8EyO1//JrZ4vz5DewWZ5vesFvcapCx2PT4GqvFx557rBaXd81hs5hxfh+Txdoj d9ktll6/yGRx8ZSrxe3GFWwWrXuPsFscftPOavHv2kYWB2GPNfPWMHq8v9HK7rFpVSebx+Yl 9R4H3+1h8ujbsorR4/MmuQD2KD2bovzSklSFjPziElulaEMLIz1DSws9IxNLPUNj81grI1Ml fTublNSczLLUIn27BL2Mc8tOMhdckqiY/uYLSwNjv2gXIyeHhICJxJxZK1m6GLk4hASWMkos 29vNBJEQk5i0bzs7hC0s8edaFxtE0SdGiXNrLjF3MXJwsAnoSexYVQhSIyKwglFi8glvkBpm gddMEkeOvmMFSQgLhEn8nfqbDcRmEVCVuPqjCWwBr4C9xM4Z26GWyUus3nCAGcTmBIr/nHYB rF5IwE5i8dGfTBMY+RYwMqxiFEktLc5Nzy020itOzC0uzUvXS87P3cQIjJ1tx35u2cHY9S74 EKMAB6MSD69DinasEGtiWXFl7iFGCQ5mJRFe269AId6UxMqq1KL8+KLSnNTiQ4ymQEdNZJYS Tc4HxnVeSbyhqaG5haWhubG5sZmFkjhvh8DBGCGB9MSS1OzU1ILUIpg+Jg5OqQZGx1DGd7uv Lp8fE6ney/3fkd922qdb3+zE3y4S+7Ve4eXT+1c5A/ZYNVt2uFhMv3by22J5JbULsVHMZjt+ M6y5o3bp7s7a2zYrOlkWdWXuePpy+edLapWrv81X4So1esJpdbo/+veyd/qPF/cH9c3yjZRz Uojcnf5wRWGVUinjjy/laucfO7FOUWIpzkg01GIuKk4EAL0oZN+zAgAA X-CMS-MailID: 20190715124441eucas1p29f1205c20e9bea5b33f8f0b5747b1102 X-Msg-Generator: CA X-RootMTR: 20190715124441eucas1p29f1205c20e9bea5b33f8f0b5747b1102 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190715124441eucas1p29f1205c20e9bea5b33f8f0b5747b1102 References: <20190715124417.4787-1-l.luba@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The ACLK100_NOC has different topology in Exynos5420 and 5422/5800. In Exynos5420 this clock divider has 3 bits while in 5422/5800 has 4 bits. The patch adds needed dividers in the exynos5800_div_clks, updates exynos5x_div_clks and exynos5420_div_clks properly. It also adds IDs to manage clocks from DT. Signed-off-by: Lukasz Luba --- drivers/clk/samsung/clk-exynos5420.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 6164d0ca75e0..c13f34d3d9a1 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -471,7 +471,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { SRC_TOP0, 4, 3), MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), - MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), + MUX(CLK_MOUT_ACLK100_NOC, "mout_aclk100_noc", mout_group1_5800_p, + SRC_TOP0, 20, 2), MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), @@ -534,6 +535,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { static const struct samsung_div_clock exynos5800_div_clks[] __initconst = { DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3), + DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", + DIV_TOP0, 20, 4), DIV(CLK_DOUT_ACLK266_ISP, "dout_aclk266_isp", "mout_aclk266_isp", DIV_TOP8, 12, 3), DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", @@ -569,7 +572,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { SRC_TOP0, 4, 2), MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), - MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), + MUX(CLK_MOUT_ACLK100_NOC, "mout_aclk100_noc", mout_group1_p, + SRC_TOP0, 20, 2), MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), MUX(0, "mout_aclk333_432_isp", mout_group4_p, @@ -600,6 +604,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3), + DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", + DIV_TOP0, 20, 3), }; static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { @@ -798,8 +804,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV_TOP0, 8, 3), DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), - DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", - DIV_TOP0, 20, 3), DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",