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Mon, 15 Jul 2019 12:44:43 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, a.hajda@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba Subject: [PATCH v1 13/50] clk: samsung: add DPLL rate table in Exynos5420 Date: Mon, 15 Jul 2019 14:43:40 +0200 Message-Id: <20190715124417.4787-14-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSaUwTQRTHnW73aKW6FoQJciQ1GrzAJn4YORQSSdYYTflkohhdYAMEWrBr VdRoUfHACoIE1EgFU5UUPKgN1oqo0IBiuFEQo1HQiHc4asQIcZdF/fZ7v/m/eS+ToTC1Gw+k 0g27OKOBzdQQSnld80T7ihjT8m0r84YxNHCjHUe1527iqG/8A44ueYSycOgzhjo6bpGo7fAX Eg2Yg5Bj6DmORiyvcdTjvkigcx0NMnTd84pEV/q6ZKirNR69zK0iUN59D4mavhzH0dTzWnms L1NjrQHM9/48knHYTxLMbdsh5tG3ehlT4LQDZswRoiO3KKNTuMz03ZwxYs0OZVrv+QdktnXu 3pHmVWYw6pMPFBSkV8EGZxkhspquArD8rTYfKAUeB/DzQD2QijEAr/6+h/3t6HF4gdRxDcD8 XNm/jj5XgVBQFEGHQ5d9p5jxo20AeiaSxAxGv5DB+nd3cfHAl14PPzbXTrOcXgR73J3Ta6jo tbDjyFG5NCwUVt96OD1YIfiJUjGjFHw3CU9Z6nEptA5Omq2kxL7wU4tzhoPg07OWmYt4aD5d CSQ+AIcKy2cyUbCppQsXl8boJfCmO0LScdB75wIhakjPgf1f54kaE7C4rgyTtAqeOKaW0mHQ aemUSewPr9WUklKEgRXFodLrFAPYMllFngGhF/7PqgDADgI4E69P5XitgdsTzrN63mRIDU/O 0juA8KOeTrWMuoC3O6kR0BTQ+KhiU5ZtU+Psbj5H3wgghWn8VDFeQalS2Jx9nDFru9GUyfGN YAEl1wSo9s96s1VNp7K7uAyOy+aMf09llCLQDDJrNEWRnQka/5HI2Sq3JThsCxxfPRDi2UAs 3nC5YFPiL52u92tSsu4gOTUYa9hsrSxp7Y+Zo3gfyf3cNMbmLo6Ua0sS1MfbP2TMtz1u1SXY 3G+HtSQW7Co0+T/zCdqYGK2vcKqejBdFpbcxKUF2R/WooosdXPiDKIg/GAffa+R8Gqtdihl5 9g9aa1gHTQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHIsWRmVeSWpSXmKPExsVy+t/xe7o2pTqxBi8WclrcWneO1WLjjPWs Fte/PGe1mH8EyO1//JrZ4vz5DewWZ5vesFvcapCx2PT4GqvFx557rBaXd81hs5hxfh+Txdoj d9ktll6/yGRx8ZSrxe3GFWwWrXuPsFscftPOavHv2kYWB2GPNfPWMHq8v9HK7rFpVSebx+Yl 9R4H3+1h8ujbsorR4/MmuQD2KD2bovzSklSFjPziElulaEMLIz1DSws9IxNLPUNj81grI1Ml fTublNSczLLUIn27BL2MKzP3sxfM46/4eMykgfETTxcjJ4eEgInE5U1fGbsYuTiEBJYySvzY 8o4JIiEmMWnfdnYIW1jiz7UuNhBbSOATo8TE2a5djBwcbAJ6EjtWFYKERQRWMEpMPuENModZ 4DWTxJGj71hBEsICnhIvj20Es1kEVCUu77oANodXwF7ifHMLC8R8eYnVGw4wg9icQPGf0y5A 7bKTWHz0J9MERr4FjAyrGEVSS4tz03OLjfSKE3OLS/PS9ZLzczcxAuNm27GfW3Ywdr0LPsQo wMGoxMPrkKIdK8SaWFZcmXuIUYKDWUmE1/YrUIg3JbGyKrUoP76oNCe1+BCjKdBRE5mlRJPz gTGdVxJvaGpobmFpaG5sbmxmoSTO2yFwMEZIID2xJDU7NbUgtQimj4mDU6qBMVts+YpvB12O f882iLI+mPNzDdfNlJbItyZ39z5XYnPYHakw0eDU0mVlz5auXKwXYhK+aUb6fL2XabWfbjf2 nv66rsnvmE3l3pfztieINiwK/vR/R5fVYcvz//x03hrsm8HdHCO76dz9tdHNTboPn7padMVv +XL6k4kVS1yy+IbVdpPWzj4RMl2JpTgj0VCLuag4EQDO9qW9sQIAAA== X-CMS-MailID: 20190715124444eucas1p2683c9896e8be45d6a0cd4afeb681a2ea X-Msg-Generator: CA X-RootMTR: 20190715124444eucas1p2683c9896e8be45d6a0cd4afeb681a2ea X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190715124444eucas1p2683c9896e8be45d6a0cd4afeb681a2ea References: <20190715124417.4787-1-l.luba@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The DPLL has fixed frequency left by the bootloader and it is not possible to change it. With this patch the DPLL gets rate table the same for the whole PLL family (similar as APLL, KPLL according to RM) so the frequency might be changed to one of the values defined there. It is needed for further patches which change the DPLL frequency to feed the clocks with proper base. It also sets CLK_IS_CRITICAL for SCLK_DPLL due to some drivers which could disable master clock, which is then populated higher and tries to disable PLL, which casues system crash. The flag is needed for this kind of use cases. Signed-off-by: Lukasz Luba --- drivers/clk/samsung/clk-exynos5420.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 7f8221527633..2395b02ce8c5 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -694,7 +694,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, CLK_SET_RATE_PARENT, 0), - MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), + MUX_F(CLK_MOUT_SCLK_DPLL, "mout_sclk_dpll", mout_dpll_p, + SRC_TOP6, 24, 1, CLK_IS_CRITICAL, 0), MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), MUX(CLK_MOUT_SW_ACLK400_ISP, "mout_sw_aclk400_isp", @@ -1514,6 +1515,7 @@ static void __init exynos5x_clk_init(struct device_node *np, if (_get_rate("fin_pll") == 24 * MHZ) { exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[dpll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; }