| Message ID | 20190715124417.4787-22-l.luba@partner.samsung.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [v1,01/50] clk: samsung: add new IDs for Exynos5420 clocks | expand |
On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote: > > Add an OPP for FSYS APB which reflects the real possible frequency. > The bus will have a new parent clock which speed has 600MHz, thus > a new possible frequency provided by the clock divider is 150MHz. > According to the documentation max possible frequency for this bus is > 200MHz. Commit msg is good but title could be improved. Focus in the title what problem/issue you are solving - add intermediate step in scaling of FSYS APB? Best regards, Krzysztof
Hi Krzysztof, On 7/17/19 10:48 AM, Krzysztof Kozlowski wrote: > On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote: >> >> Add an OPP for FSYS APB which reflects the real possible frequency. >> The bus will have a new parent clock which speed has 600MHz, thus >> a new possible frequency provided by the clock divider is 150MHz. >> According to the documentation max possible frequency for this bus is >> 200MHz. > > Commit msg is good but title could be improved. Focus in the title > what problem/issue you are solving - add intermediate step in scaling > of FSYS APB? The devfreq governor for this bus device follows the set OPP of the master device - WCORE bus and sets the OPP with corresponding ID. Thus, jumping to max frequency 200MHz when the WCORE bus and other devices are operating in the middle of their min-max speed is not needed for FSYS APB and this patch adds the intermediate speed step. Regards, Lukasz > > Best regards, > Krzysztof > >
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index c7fc4b829b2a..2b36c2f77a10 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -1153,6 +1153,9 @@ opp-hz = /bits/ 64 <100000000>; }; opp01 { + opp-hz = /bits/ 64 <150000000>; + }; + opp02 { opp-hz = /bits/ 64 <200000000>; }; };
Add an OPP for FSYS APB which reflects the real possible frequency. The bus will have a new parent clock which speed has 600MHz, thus a new possible frequency provided by the clock divider is 150MHz. According to the documentation max possible frequency for this bus is 200MHz. Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> --- arch/arm/boot/dts/exynos5420.dtsi | 3 +++ 1 file changed, 3 insertions(+)