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Mon, 15 Jul 2019 12:44:52 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, a.hajda@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba Subject: [PATCH v1 24/50] ARM: dts: exynos: align OPPs with PLL rate for MSCL in Exynos5420 Date: Mon, 15 Jul 2019 14:43:51 +0200 Message-Id: <20190715124417.4787-25-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSeUhUURTGu+/NW1wmXqPoRUVroMw0NSm4YLlQxiAt0j9BYTrqw6WZ0eap ZYqNppWDS1mZhKaF4Z7b4KiZTKM4lLmVubaRQWBmhkuJoc3jTfTf737nO985HC6NSzoJJzpe lcyqVXKFlLQWtfevDe09muIV7mtqY9D0kyECtZQ2EWhi+SuBKvrMz6LZbzgaHm6m0GD2PIWm NS6odXacQD/zPxDoTVcZiUqHezDU2PeeQo8nRjE0+jIEzWTVkCj3WR+FeuevE2hjvEUUZCdr eNAAZD8mcylZa10eKWuruiJ7vtCNyQp1dUC21OoaRp2xPhjDKuJTWbVPQKR13OrvbDJpir60 mV0ENOAtqQU0DZn98G7BaS2woiVMDYAvmo9pgbWZlwE0DJcD4bEEYOdsFsa7+IYe7WtM6KgG sKcgQ2Bzx7un/nwoyXjDjroLvGzPVAHYtxbF5+DMFAa7v3QSfMGOCYeT3esinkXMTjhxq4Pk WcwEQq3+s0iY5Qbrmw04z1Zmfa1khOSDIDNEwaqKGlwwHYE9q/2W5ezgnElHCewCB27nW4I4 qCl4CATOgLNF5RaPP+w1jRL80jjjAZu6fAQ5GC5fzaOEA22Fk9+38TJuxuL2e7ggi+GNaxLB vRvq8kcsCzjA6oYSS7gM6gfu4MJ1igFcb8JuArf7/2dVAlAHHNkUThnLcn4q9qI3J1dyKapY 7+hEZSswf6iBDdNyB+j6E2UEDA2ktuKgGM9wCSFP5dKURgBpXGovPrRilsQx8rTLrDoxQp2i YDkjcKZFUkdx+pZPZyVMrDyZPc+ySaz6XxWjrZw0IC59JHRu6pdh1Y9MXcwNH2QVAZV6vXtD TFjmRHDZUt6UsevAyQSHzFcKjxylyVAw5ntqJZ7YsUg5T+fM6GoN0QkbNiNWgVX1h0NmFo57 ebuOql2bI7kxG4OJnlsq3O6CeUaMdRRu/ei+eUKl09tmYUHnGotjQ2sbK3cZH3W2S0VcnHzf HlzNyf8CfRx3+EwDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAIsWRmVeSWpSXmKPExsVy+t/xe7qupTqxBu/eiVjcWneO1WLjjPWs Fte/PGe1mH8EyO1//JrZ4vz5DewWZ5vesFvcapCx2PT4GqvFx557rBaXd81hs5hxfh+Txdoj d9ktll6/yGRx8ZSrxe3GFWwWrXuPsFscftPOavHv2kYWB2GPNfPWMHq8v9HK7rFpVSebx+Yl 9R4H3+1h8ujbsorR4/MmuQD2KD2bovzSklSFjPziElulaEMLIz1DSws9IxNLPUNj81grI1Ml fTublNSczLLUIn27BL2Mbz+a2ApuclT8b+pnbGC8ytbFyMkhIWAisa/rElMXIxeHkMBSRolT 3/ezQiTEJCbt284OYQtL/LnWxQZR9IlR4vidH0BFHBxsAnoSO1YVgtSICKxglJh8whukhlng NZPEkaPvwAYJC0RL7Ny8D2wbi4CqxPWJO8BsXgF7ia7tj1ggFshLrN5wgBnE5gSK/5x2AaxG SMBOYvHRn0wTGPkWMDKsYhRJLS3OTc8tNtQrTswtLs1L10vOz93ECIydbcd+bt7BeGlj8CFG AQ5GJR5ehxTtWCHWxLLiytxDjBIczEoivLZfgUK8KYmVValF+fFFpTmpxYcYTYGOmsgsJZqc D4zrvJJ4Q1NDcwtLQ3Njc2MzCyVx3g6BgzFCAumJJanZqakFqUUwfUwcnFINjP7+a5gcfWze s7k/fyP555Tv4Tbn4qnvjbSMptbre1QkhUv9SqzQ2lexhVeZ9+LVf2amsrlb4xncPV9z7p3i c2B/56LA3ruXpDbeXq1/SnWxY+dm378nNYp+G0oE5MWmTer9Hrk0dXNHoyzXr6W7OY58Obbg qtZzOeazp/ZZX98ePGu2XaySphJLcUaioRZzUXEiABubiwmzAgAA X-CMS-MailID: 20190715124453eucas1p1dbdfab862499d9a7bd8a853e30944bac X-Msg-Generator: CA X-RootMTR: 20190715124453eucas1p1dbdfab862499d9a7bd8a853e30944bac X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190715124453eucas1p1dbdfab862499d9a7bd8a853e30944bac References: <20190715124417.4787-1-l.luba@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The OPPs must reflect possible values after dividing the master clock. The old values 400 and 333, 222, etc does not have common parent rate. Thus, align the values to parent rate such that they will be set exactly using only a divider. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5420.dtsi | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 0739e7bd4628..74d014f3eaa6 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -1336,18 +1336,15 @@ compatible = "operating-points-v2"; opp00 { - opp-hz = /bits/ 64 <84000000>; + opp-hz = /bits/ 64 <150000000>; }; opp01 { - opp-hz = /bits/ 64 <167000000>; + opp-hz = /bits/ 64 <200000000>; }; opp02 { - opp-hz = /bits/ 64 <222000000>; + opp-hz = /bits/ 64 <300000000>; }; opp03 { - opp-hz = /bits/ 64 <333000000>; - }; - opp04 { opp-hz = /bits/ 64 <400000000>; }; };