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Mon, 15 Jul 2019 12:45:03 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, a.hajda@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba Subject: [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422 Date: Mon, 15 Jul 2019 14:44:04 +0200 Message-Id: <20190715124417.4787-38-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSaUhUYRSG++auihPXUfSgWTRROC2aEvRhaQZZ91fYX6Ny0ouJjstcrVyo KcoNyzArW63QrNEyzdRWRxuSMh21csUKFyRTJxslTJTmdqf6957nvO974ONjCdUzyouNTUgR 9AnaeDXtTNa9nmvfEJ66ft/GnsdBuP9BO4Wri6so3DMzRuESs30sGP5GYIvlIYPbTk4wuN+w DNcMd1N4Ov8Thd8/vUbjYstLBb5vHmRwWU+nAne+DcMDJ+7S+PQLM4NfTWRTeLG7mgx14ytv VCLe2nua4WuMuTT/qPQ43zT1XMGfrTUi3lazPJyJcN4aLcTHHhb0/iGRzoduZOXTSRbmaM5t CzKgBjoPObHAbYL6+nEiDzmzKu4ugrLxClIeZhC8sVoVkkvF2RBUjWr+Jj6P9joS5Qje9WQT /xIluVftCZalOT9oMCZLAXeuFIF57qDkIbg+BTwfeUJJCzduP5gWbaTkJ7nVUNToImEltw1+ WptI+dgKqHhoIiTtZOdzFztoqQe4LgaKbB8oKQvcDig3ecp+NxhvqWVkvQxaz+c7ekQwnLmF ZJ0JwwXXHZ4t8Kql808NwWmg6qm/jLfDhY4xR/tS6J10lTBhl4V1lwgZKyEnSyW7faE2v0Mh aw8or7zoKOfB2leM5McpRLDQ9oA+h1Zc+X/sJkJG5CmkiroYQQxIEI74iVqdmJoQ4xeVqKtB 9i/VutjyowHNdh1sRhyL1C7K0Oh1+1SU9rCYpmtGwBJqd2XwrB0po7Vp6YI+8YA+NV4Qm5E3 S6o9lRlLvuxVcTHaFCFOEJIE/d+tgnXyMqA14QOwedr8sSku40XsXOCu6csjrgdWVUcAGfus mMy5Z5g0WQr7jqu6jlo8cnYGRg0c81yu6/cuWRr8YybSV0zXNOYlPyk0Zv/0mOK/7mkrsGnG Egc18z5DvYZy97Nh8+3V1zODVg6F7I46dX/lne7AX9+9fQwm49fAhW/zmptvhtWkeEgbsJbQ i9rfl/no+E4DAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprPIsWRmVeSWpSXmKPExsVy+t/xe7oBpTqxBtuuCFvcWneO1WLjjPWs Fte/PGe1mH8EyO1//JrZ4vz5DewWZ5vesFvcapCx2PT4GqvFx557rBaXd81hs5hxfh+Txdoj d9ktll6/yGRx8ZSrxe3GFWwWrXuPsFscftPOavHv2kYWB2GPNfPWMHq8v9HK7rFpVSebx+Yl 9R4H3+1h8ujbsorR4/MmuQD2KD2bovzSklSFjPziElulaEMLIz1DSws9IxNLPUNj81grI1Ml fTublNSczLLUIn27BL2MeW09bAXn2Ss6Fp1nbGDcwdbFyMkhIWAicf/pDeYuRi4OIYGljBKr rmxihEiISUzat50dwhaW+HOtiw2i6BOjxPcfDUAdHBxsAnoSO1YVgtSICKxglJh8whukhlng NZPEkaPvWEESwgIxEr+/zGICqWcRUJWYsp8HJMwrYC/x/f1BFoj58hKrNxxgBrE5geI/p10A O05IwE5i8dGfTBMY+RYwMqxiFEktLc5Nzy020itOzC0uzUvXS87P3cQIjJxtx35u2cHY9S74 EKMAB6MSD69DinasEGtiWXFl7iFGCQ5mJRFe269AId6UxMqq1KL8+KLSnNTiQ4ymQDdNZJYS Tc4HRnVeSbyhqaG5haWhubG5sZmFkjhvh8DBGCGB9MSS1OzU1ILUIpg+Jg5OqQZG+SmZYUc5 HDoK5li+r+fwtzxav0tD0K91aYogl4DPLj0D37/7HCZuj+HZtSku8XngYbO2/67fFISWWPE6 ivbp6s4+nzOd16Zp59XfnB9bvxhdP1ww22xlXsjLFcuYVDTdVZJnaHezlclXRRYdfSHKbHcz KvHLP8ce7spZTxw//Qz4c2S7zQElluKMREMt5qLiRACNe08esgIAAA== X-CMS-MailID: 20190715124504eucas1p1afe0da2c6ac3a8b45d85017a77ba9edf X-Msg-Generator: CA X-RootMTR: 20190715124504eucas1p1afe0da2c6ac3a8b45d85017a77ba9edf X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190715124504eucas1p1afe0da2c6ac3a8b45d85017a77ba9edf References: <20190715124417.4787-1-l.luba@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The FSYS bus OPP table has been aligned to the new parent rate. This patch sets the proper parent and picks the init frequency before the devfreq governor starts working. It sets also parent rate (DPLL to 1200MHz). Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index d460041f716c..6a82dd175b8a 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -72,6 +72,11 @@ &bus_fsys { devfreq = <&bus_wcore>; + assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>, + <&clock CLK_DOUT_ACLK200_FSYS>, + <&clock CLK_FOUT_DPLL>; + assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>; + assigned-clock-rates = <0>, <240000000>,<1200000000>; status = "okay"; };