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Thu, 8 Aug 2019 09:02:50 +0000 (GMT) From: Kamil Konieczny To: k.konieczny@partner.samsung.com Cc: Marek Szyprowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi , Krzysztof Kozlowski , Kukjin Kim , Kyungmin Park , Mark Rutland , MyungJoo Ham , Nishanth Menon , Rob Herring , Stephen Boyd , Viresh Kumar , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [RESEND PATCH v5 3/4] ARM: dts: exynos: add initial data for coupled regulators for Exynos5422/5800 Date: Thu, 8 Aug 2019 11:02:33 +0200 Message-Id: <20190808090234.12577-4-k.konieczny@partner.samsung.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190808090234.12577-1-k.konieczny@partner.samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Sa0hTYRj2O5ed43B6Ogq+Zhda9aMi7UofNaKgYCFB+KMfhdWqk1k6106a 2o82K7NlFl3Illc0klGaq7RWKdlwi3lBLTO6TU3F0sImlWDazo5R/573eZ6X53nhZUn+LT2T TdIfFYx6XbJaoaRqm8Zbl2r64xKWDXWocU1BNY1fjw3SuMTZSuP8+imEL/R9IXFb210Gt2QP M9je10XjTkehAvvOOxEuaKsn8B3newbffN1O4LfmSgUe/tVC4NNPnQye7Kqh8D1vk2IDr71d fBtp7bazCu29ihPaZ1+fENr8+zakdXXXEVqffc42ZodSs19ITkoXjLHr9ygPur9tNbg1GYWl w4wJdcdYEMMCtwpOL7EgJctzlQjKm64iCwr2D2MI8gqzZMGH4HnDOCkJkt/x7RUpC7cQWIrL aXnwb/Rd8QVcCm4N9NY1ExKO4ObD5Q/XAhskN06Bx3GSloRwTg+f3T2BPIpbCL3eosCCitsE n5qvK+S4uXD24WNKwsHcZrhje0HJnhnw4vqnACb9npMPbkzXG2GgwcnIeBNUlVdP8+Hw2XV/ mp8FU49KCBkfg/6yfEYqB9wpBN4zo5QsrIPnrnZ/UdYfsAiqHbEyvREmRj2URAMXCt0jM+QK oXCpVrpRolWQm8PL7qVQPNVMyzgaLFNV01gL2ZPfyYtonvW/Y6z/HWP9l1uKSBuKFNLElERB XKEXjsWIuhQxTZ8Ysy81xY78L+eZdI09RI6JvY2IY5E6RGVwxyXwtC5dzExpRMCS6gjVh/Qt Cbxqvy4zSzCm7jamJQtiI4pmKXWk6niQdyfPJeqOCocFwSAY/6oEGzzThC7mmDsKftrNxyFz 4t2c3KCe+JW8sm4km0gfqDhsSl69a2HNy3eJ4sdndNo6U5RZyedU9jTEZ4QNlSnyDkR4bAv2 9r+K1mt8RYOpNYZznpDZP25sNXxf4ey1OpXDR37kPTpwJqlqY6tvlHqzfe1A7qGoMN5a2xJS 3Jn/+8TisEMtako8qFu+mDSKuj/xhvZ3bgMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrLIsWRmVeSWpSXmKPExsVy+t/xe7rWT71jDeZ90bHYOGM9q8X1L89Z LeYfOcdq0bfvP6NF/+PXzBbnz29gtzjb9IbdYtPja6wWl3fNYbP43HuE0WLG+X1MFmuP3GW3 WHr9IpPF7cYVbBZvfpxlsmjde4Td4t+1jSwWmx8cY3MQ8lgzbw2jx6ZVnWwem5fUexx8t4fJ o2/LKkaP4ze2M3l83iQXwB6lZ1OUX1qSqpCRX1xiqxRtaGGkZ2hpoWdkYqlnaGwea2VkqqRv Z5OSmpNZllqkb5egl3HivW/BCZuKOQvesDcw3tDrYuTkkBAwkdj1/ipzFyMXh5DAUkaJDce3 MUIkpCUaT69mgrCFJf5c62KDKPrEKLH06Qo2kASbgLnEo+1nwIpEBJQlJt+bDjaJWaCTVWLJ pL/sIAlhgRyJuT8XgDWwCKhKPHowF6yBV8BF4smZmWwQG+QlOnfsZgGxOQVcJdauOglmCwHV bHx/nRWiXlDi5MwnYHFmoPrmrbOZJzAKzEKSmoUktYCRaRWjSGppcW56brGRXnFibnFpXrpe cn7uJkZgVG479nPLDsaud8GHGAU4GJV4eAtOeMcKsSaWFVfmHmKU4GBWEuG9V+YZK8SbklhZ lVqUH19UmpNafIjRFOiJicxSosn5wISRVxJvaGpobmFpaG5sbmxmoSTO2yFwMEZIID2xJDU7 NbUgtQimj4mDU6qB8XDggbS5Helhycd8Hp8/OW3GNg+7+kX7YzwvfupfYx7J7iPZcvuWomF6 7MJ9SxknHnuSGvKc6YjVy0em71+6G1mn/mbd4HR7dt3h+VWfnMI6BNZ86Ms2e+4nsTT8TMU5 7+rcGYtSUpbnMtck3k+SyW+INn+0cJbwPD39I2v+7vZhFxZ/eMsvV4mlOCPRUIu5qDgRAPma MtbgAgAA X-CMS-MailID: 20190808090252eucas1p2afec3e288965bb7e7aa6f96f67686273 X-Msg-Generator: CA X-RootMTR: 20190808090252eucas1p2afec3e288965bb7e7aa6f96f67686273 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190808090252eucas1p2afec3e288965bb7e7aa6f96f67686273 References: <20190808090234.12577-1-k.konieczny@partner.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Marek Szyprowski Declare Exynos5422/5800 voltage ranges for opp points for big cpu core and bus wcore and couple their voltage supllies as vdd_arm and vdd_int should be in 300mV range. Signed-off-by: Marek Szyprowski [k.konieczny: add missing patch description] Signed-off-by: Kamil Konieczny Reviewed-by: Chanwoo Choi --- arch/arm/boot/dts/exynos5420.dtsi | 34 +++++++++---------- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 4 +++ arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 +++ arch/arm/boot/dts/exynos5800.dtsi | 32 ++++++++--------- 4 files changed, 41 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 5fb2326875dc..0cbf74750553 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -48,62 +48,62 @@ opp-shared; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1250000>; + opp-microvolt = <1250000 1250000 1500000>; clock-latency-ns = <140000>; }; opp-1700000000 { opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <1212500>; + opp-microvolt = <1212500 1212500 1500000>; clock-latency-ns = <140000>; }; opp-1600000000 { opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <1175000>; + opp-microvolt = <1175000 1175000 1500000>; clock-latency-ns = <140000>; }; opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1137500>; + opp-microvolt = <1137500 1137500 1500000>; clock-latency-ns = <140000>; }; opp-1400000000 { opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1112500>; + opp-microvolt = <1112500 1112500 1500000>; clock-latency-ns = <140000>; }; opp-1300000000 { opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1062500>; + opp-microvolt = <1062500 1062500 1500000>; clock-latency-ns = <140000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1037500>; + opp-microvolt = <1037500 1037500 1500000>; clock-latency-ns = <140000>; }; opp-1100000000 { opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1012500>; + opp-microvolt = <1012500 1012500 1500000>; clock-latency-ns = <140000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = < 987500>; + opp-microvolt = < 987500 987500 1500000>; clock-latency-ns = <140000>; }; opp-900000000 { opp-hz = /bits/ 64 <900000000>; - opp-microvolt = < 962500>; + opp-microvolt = < 962500 962500 1500000>; clock-latency-ns = <140000>; }; opp-800000000 { opp-hz = /bits/ 64 <800000000>; - opp-microvolt = < 937500>; + opp-microvolt = < 937500 937500 1500000>; clock-latency-ns = <140000>; }; opp-700000000 { opp-hz = /bits/ 64 <700000000>; - opp-microvolt = < 912500>; + opp-microvolt = < 912500 912500 1500000>; clock-latency-ns = <140000>; }; }; @@ -1100,23 +1100,23 @@ opp00 { opp-hz = /bits/ 64 <84000000>; - opp-microvolt = <925000>; + opp-microvolt = <925000 925000 1400000>; }; opp01 { opp-hz = /bits/ 64 <111000000>; - opp-microvolt = <950000>; + opp-microvolt = <950000 950000 1400000>; }; opp02 { opp-hz = /bits/ 64 <222000000>; - opp-microvolt = <950000>; + opp-microvolt = <950000 950000 1400000>; }; opp03 { opp-hz = /bits/ 64 <333000000>; - opp-microvolt = <950000>; + opp-microvolt = <950000 950000 1400000>; }; opp04 { opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <987500>; + opp-microvolt = <987500 987500 1400000>; }; }; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 25d95de15c9b..65d094256b54 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -428,6 +428,8 @@ regulator-max-microvolt = <1500000>; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&buck3_reg>; + regulator-coupled-max-spread = <300000>; }; buck3_reg: BUCK3 { @@ -436,6 +438,8 @@ regulator-max-microvolt = <1400000>; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&buck2_reg>; + regulator-coupled-max-spread = <300000>; }; buck4_reg: BUCK4 { diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index e0f470fe54c8..5c1e965ed7e9 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -257,6 +257,8 @@ regulator-always-on; regulator-boot-on; regulator-ramp-delay = <12500>; + regulator-coupled-with = <&buck3_reg>; + regulator-coupled-max-spread = <300000>; regulator-state-mem { regulator-off-in-suspend; }; @@ -269,6 +271,8 @@ regulator-always-on; regulator-boot-on; regulator-ramp-delay = <12500>; + regulator-coupled-with = <&buck2_reg>; + regulator-coupled-max-spread = <300000>; regulator-state-mem { regulator-off-in-suspend; }; diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi index 57d3b319fd65..2a74735d161c 100644 --- a/arch/arm/boot/dts/exynos5800.dtsi +++ b/arch/arm/boot/dts/exynos5800.dtsi @@ -22,61 +22,61 @@ &cluster_a15_opp_table { opp-1700000000 { - opp-microvolt = <1250000>; + opp-microvolt = <1250000 1250000 1500000>; }; opp-1600000000 { - opp-microvolt = <1250000>; + opp-microvolt = <1250000 1250000 1500000>; }; opp-1500000000 { - opp-microvolt = <1100000>; + opp-microvolt = <1100000 1100000 1500000>; }; opp-1400000000 { - opp-microvolt = <1100000>; + opp-microvolt = <1100000 1100000 1500000>; }; opp-1300000000 { - opp-microvolt = <1100000>; + opp-microvolt = <1100000 1100000 1500000>; }; opp-1200000000 { - opp-microvolt = <1000000>; + opp-microvolt = <1000000 1000000 1500000>; }; opp-1100000000 { - opp-microvolt = <1000000>; + opp-microvolt = <1000000 1000000 1500000>; }; opp-1000000000 { - opp-microvolt = <1000000>; + opp-microvolt = <1000000 1000000 1500000>; }; opp-900000000 { - opp-microvolt = <1000000>; + opp-microvolt = <1000000 1000000 1500000>; }; opp-800000000 { - opp-microvolt = <900000>; + opp-microvolt = <900000 900000 1500000>; }; opp-700000000 { - opp-microvolt = <900000>; + opp-microvolt = <900000 900000 1500000>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000>; + opp-microvolt = <900000 900000 1500000>; clock-latency-ns = <140000>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <900000>; + opp-microvolt = <900000 900000 1500000>; clock-latency-ns = <140000>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <900000>; + opp-microvolt = <900000 900000 1500000>; clock-latency-ns = <140000>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; + opp-microvolt = <900000 900000 1500000>; clock-latency-ns = <140000>; }; opp-200000000 { opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000>; + opp-microvolt = <900000 900000 1500000>; clock-latency-ns = <140000>; }; };