From patchwork Mon Sep 23 16:14:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 11157273 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7A71B112B for ; Mon, 23 Sep 2019 16:14:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 591C421928 for ; Mon, 23 Sep 2019 16:14:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569255297; bh=qXqV0J88N2dypvGBO7A/lZfZUOS9/+hk7Rbjthl+2/U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=PPRz5kOTJ0JnZZOU7Sz+AIlA7xcYcARzZDd6gXCg/C697mIQVpf0I/IOLzFdlmkda 7j8IimSMM7Ce4bCrLwkGwiK09ZYgqNhsIR6RS4NLfJ2vDGlCqpbWCJenpkGsO0kKvQ qUqRFtfhrPKMSyIDbHs41E+b/ZW8QobT+pN4OYjo= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2437658AbfIWQO4 (ORCPT ); Mon, 23 Sep 2019 12:14:56 -0400 Received: from mail.kernel.org ([198.145.29.99]:59196 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2395236AbfIWQO4 (ORCPT ); Mon, 23 Sep 2019 12:14:56 -0400 Received: from localhost.localdomain (unknown [194.230.155.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 48A7F20B7C; Mon, 23 Sep 2019 16:14:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1569255295; bh=qXqV0J88N2dypvGBO7A/lZfZUOS9/+hk7Rbjthl+2/U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HSgzdn01o5ejN576RO+vqEPDnxHhjrna19PWbCUd2zXNLjFC1QnsYCWkiYH8VT0rb 2Grlxp+4Rad0kYSiRLsC6HLh7IpYUr+SPtegbvff5omkvf5pTvDqJ+8d1QPyxCEPfP dRqokgYw+O0yLG7WzUkTjBcF8HpkwBNkHVAtI/4U= From: Krzysztof Kozlowski To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Mark Rutland , Kukjin Kim , Krzysztof Kozlowski , Marek Szyprowski , Andrzej Hajda , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Cc: Sylwester Nawrocki Subject: [PATCH v4 8/8] ARM: dts: exynos: Use defines for MCT interrupt GIC SPI/PPI specifier Date: Mon, 23 Sep 2019 18:14:11 +0200 Message-Id: <20190923161411.9236-8-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190923161411.9236-1-krzk@kernel.org> References: <20190923161411.9236-1-krzk@kernel.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Replace hard-coded number with appropriate define for GIC SPI or PPI specifier in interrupt. This makes code easier to read. No expected functionality change. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210.dtsi | 8 ++++---- arch/arm/boot/dts/exynos4412.dtsi | 4 ++-- arch/arm/boot/dts/exynos5250.dtsi | 4 ++-- arch/arm/boot/dts/exynos54xx.dtsi | 16 ++++++++-------- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 5fa33d43821e..aac3b7a20a37 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -111,12 +111,12 @@ reg = <0x10050000 0x800>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; - interrupts-extended = <&gic 0 57 IRQ_TYPE_LEVEL_HIGH>, - <&gic 0 69 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, <&combiner 12 6>, <&combiner 12 7>, - <&gic 0 42 IRQ_TYPE_LEVEL_HIGH>, - <&gic 0 48 IRQ_TYPE_LEVEL_HIGH>; + <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; }; watchdog: watchdog@10060000 { diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 9b5fb4e54d7c..96a5ef3a2864 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -248,11 +248,11 @@ reg = <0x10050000 0x800>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; - interrupts-extended = <&gic 0 57 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, <&combiner 12 5>, <&combiner 12 6>, <&combiner 12 7>, - <&gic 1 12 IRQ_TYPE_LEVEL_HIGH>; + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; }; watchdog: watchdog@10060000 { diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index a549eafd2c64..f01e3156191d 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -242,8 +242,8 @@ <&combiner 23 4>, <&combiner 25 2>, <&combiner 25 3>, - <&gic 0 120 IRQ_TYPE_LEVEL_HIGH>, - <&gic 0 121 IRQ_TYPE_LEVEL_HIGH>; + <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; }; pinctrl_0: pinctrl@11400000 { diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index aca1b4831e38..06ae40a2f1e9 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -71,14 +71,14 @@ <&combiner 23 4>, <&combiner 25 2>, <&combiner 25 3>, - <&gic 0 120 IRQ_TYPE_LEVEL_HIGH>, - <&gic 0 121 IRQ_TYPE_LEVEL_HIGH>, - <&gic 0 122 IRQ_TYPE_LEVEL_HIGH>, - <&gic 0 123 IRQ_TYPE_LEVEL_HIGH>, - <&gic 0 128 IRQ_TYPE_LEVEL_HIGH>, - <&gic 0 129 IRQ_TYPE_LEVEL_HIGH>, - <&gic 0 130 IRQ_TYPE_LEVEL_HIGH>, - <&gic 0 131 IRQ_TYPE_LEVEL_HIGH>; + <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; }; watchdog: watchdog@101d0000 {