| Message ID | 20200403111511.10598-1-hyunki00.koo@samsung.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v4] tty: samsung_tty: 32-bit access for TX/RX hold registers | expand |
On Fri, Apr 03, 2020 at 08:15:10PM +0900, Hyunki Koo wrote: > Support 32-bit access for the TX/RX hold registers UTXH and URXH. > > This is required for some newer SoCs. > > Signed-off-by: Hyunki Koo <hyunki00.koo@samsung.com> > --- > v2: > line 954 : change rd_regl to rd_reg in for backward compatibility. > line 2031: Add init value for ourport->port.iotype to UPIO_MEM > v3: > line 2031: remove redundant init value for ourport->port.iotype > v4: > correct variable types and change misleading function name > --- > drivers/tty/serial/samsung_tty.c | 76 +++++++++++++++++++++++++++++++++------- > 1 file changed, 64 insertions(+), 12 deletions(-) > > diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c > index 73f951d65b93..bdf1d4d12cb1 100644 > --- a/drivers/tty/serial/samsung_tty.c > +++ b/drivers/tty/serial/samsung_tty.c > @@ -154,12 +154,47 @@ struct s3c24xx_uart_port { > #define portaddrl(port, reg) \ > ((unsigned long *)(unsigned long)((port)->membase + (reg))) > > -#define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg))) > +static u32 rd_reg(struct uart_port *port, u32 reg) > +{ > + switch (port->iotype) { > + case UPIO_MEM: > + return readb_relaxed(portaddr(port, reg)); > + case UPIO_MEM32: > + return readl_relaxed(portaddr(port, reg)); > + default: > + return 0; > + } > + return 0; > +} > + > #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) > > -#define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg)) > +static void wr_reg(struct uart_port *port, u32 reg, u32 val) > +{ > + switch (port->iotype) { > + case UPIO_MEM: > + writeb_relaxed(val, portaddr(port, reg)); > + break; > + case UPIO_MEM32: > + writel_relaxed(val, portaddr(port, reg)); > + break; > + } > +} > + > #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) > > +static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val) > +{ > + switch (port->iotype) { > + case UPIO_MEM: > + writeb(val, portaddr(port, reg)); > + break; > + case UPIO_MEM32: > + writel(val, portaddr(port, reg)); > + break; > + } > +} why do you have a default for the read function, but not the write functions? > + > /* Byte-order aware bit setting/clearing functions. */ > > static inline void s3c24xx_set_bit(struct uart_port *port, int idx, > @@ -714,7 +749,7 @@ static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport) > fifocnt--; > > uerstat = rd_regl(port, S3C2410_UERSTAT); > - ch = rd_regb(port, S3C2410_URXH); > + ch = rd_reg(port, S3C2410_URXH); > > if (port->flags & UPF_CONS_FLOW) { > int txe = s3c24xx_serial_txempty_nofifo(port); > @@ -826,7 +861,7 @@ static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) > } > > if (port->x_char) { > - wr_regb(port, S3C2410_UTXH, port->x_char); > + wr_reg(port, S3C2410_UTXH, port->x_char); > port->icount.tx++; > port->x_char = 0; > goto out; > @@ -852,7 +887,7 @@ static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) > if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) > break; > > - wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]); > + wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]); > xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); > port->icount.tx++; > count--; > @@ -916,7 +951,7 @@ static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) > /* no modem control lines */ > static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) > { > - unsigned int umstat = rd_regb(port, S3C2410_UMSTAT); > + unsigned int umstat = rd_reg(port, S3C2410_UMSTAT); > > if (umstat & S3C2410_UMSTAT_CTS) > return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; > @@ -1974,7 +2009,7 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) > struct device_node *np = pdev->dev.of_node; > struct s3c24xx_uart_port *ourport; > int index = probe_index; > - int ret; > + int ret, prop = 0; > > if (np) { > ret = of_alias_get_id(np, "serial"); > @@ -2000,10 +2035,27 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) > dev_get_platdata(&pdev->dev) : > ourport->drv_data->def_cfg; > > - if (np) > + if (np) { > of_property_read_u32(np, > "samsung,uart-fifosize", &ourport->port.fifosize); > > + if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { > + switch (prop) { > + case 1: > + ourport->port.iotype = UPIO_MEM; > + break; > + case 4: > + ourport->port.iotype = UPIO_MEM32; > + break; > + default: > + dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n", > + prop); > + ret = -EINVAL; > + break; > + } > + } > + } If the property is not there, the type will be uninitialized and no warning will be spit out, are you sure you want to do that? Can you break this into 2 patches, one that changes the names of the macros and the calls to them, and the second that adds the new functionality? That way it's easier to review/read. thanks, greg k-h
On Fri, Apr 03, 2020 at 01:42:37PM +0200, Greg KH wrote: > On Fri, Apr 03, 2020 at 08:15:10PM +0900, Hyunki Koo wrote: > > Support 32-bit access for the TX/RX hold registers UTXH and URXH. > > > > This is required for some newer SoCs. > > > > Signed-off-by: Hyunki Koo <hyunki00.koo@samsung.com> > > --- > > v2: > > line 954 : change rd_regl to rd_reg in for backward compatibility. > > line 2031: Add init value for ourport->port.iotype to UPIO_MEM > > v3: > > line 2031: remove redundant init value for ourport->port.iotype > > v4: > > correct variable types and change misleading function name > > --- > > drivers/tty/serial/samsung_tty.c | 76 +++++++++++++++++++++++++++++++++------- > > 1 file changed, 64 insertions(+), 12 deletions(-) > > > > diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c > > index 73f951d65b93..bdf1d4d12cb1 100644 > > --- a/drivers/tty/serial/samsung_tty.c > > +++ b/drivers/tty/serial/samsung_tty.c > > @@ -154,12 +154,47 @@ struct s3c24xx_uart_port { > > #define portaddrl(port, reg) \ > > ((unsigned long *)(unsigned long)((port)->membase + (reg))) > > > > -#define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg))) > > +static u32 rd_reg(struct uart_port *port, u32 reg) > > +{ > > + switch (port->iotype) { > > + case UPIO_MEM: > > + return readb_relaxed(portaddr(port, reg)); > > + case UPIO_MEM32: > > + return readl_relaxed(portaddr(port, reg)); > > + default: > > + return 0; > > + } > > + return 0; > > +} > > + > > #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) > > > > -#define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg)) > > +static void wr_reg(struct uart_port *port, u32 reg, u32 val) > > +{ > > + switch (port->iotype) { > > + case UPIO_MEM: > > + writeb_relaxed(val, portaddr(port, reg)); > > + break; > > + case UPIO_MEM32: > > + writel_relaxed(val, portaddr(port, reg)); > > + break; > > + } > > +} > > + > > #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) > > > > +static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val) > > +{ > > + switch (port->iotype) { > > + case UPIO_MEM: > > + writeb(val, portaddr(port, reg)); > > + break; > > + case UPIO_MEM32: > > + writel(val, portaddr(port, reg)); > > + break; > > + } > > +} > > why do you have a default for the read function, but not the write > functions? The default for read will never happen and it returns bogus value just to satisfy the compiler. That's my understanding. What would you like to do for writes()? Print error msg? No point, it should not happen because of check in probe(). > > > + > > /* Byte-order aware bit setting/clearing functions. */ > > > > static inline void s3c24xx_set_bit(struct uart_port *port, int idx, > > @@ -714,7 +749,7 @@ static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport) > > fifocnt--; > > > > uerstat = rd_regl(port, S3C2410_UERSTAT); > > - ch = rd_regb(port, S3C2410_URXH); > > + ch = rd_reg(port, S3C2410_URXH); > > > > if (port->flags & UPF_CONS_FLOW) { > > int txe = s3c24xx_serial_txempty_nofifo(port); > > @@ -826,7 +861,7 @@ static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) > > } > > > > if (port->x_char) { > > - wr_regb(port, S3C2410_UTXH, port->x_char); > > + wr_reg(port, S3C2410_UTXH, port->x_char); > > port->icount.tx++; > > port->x_char = 0; > > goto out; > > @@ -852,7 +887,7 @@ static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) > > if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) > > break; > > > > - wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]); > > + wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]); > > xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); > > port->icount.tx++; > > count--; > > @@ -916,7 +951,7 @@ static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) > > /* no modem control lines */ > > static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) > > { > > - unsigned int umstat = rd_regb(port, S3C2410_UMSTAT); > > + unsigned int umstat = rd_reg(port, S3C2410_UMSTAT); > > > > if (umstat & S3C2410_UMSTAT_CTS) > > return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; > > @@ -1974,7 +2009,7 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) > > struct device_node *np = pdev->dev.of_node; > > struct s3c24xx_uart_port *ourport; > > int index = probe_index; > > - int ret; > > + int ret, prop = 0; > > > > if (np) { > > ret = of_alias_get_id(np, "serial"); > > @@ -2000,10 +2035,27 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) > > dev_get_platdata(&pdev->dev) : > > ourport->drv_data->def_cfg; > > > > - if (np) > > + if (np) { > > of_property_read_u32(np, > > "samsung,uart-fifosize", &ourport->port.fifosize); > > > > + if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { > > + switch (prop) { > > + case 1: > > + ourport->port.iotype = UPIO_MEM; > > + break; > > + case 4: > > + ourport->port.iotype = UPIO_MEM32; > > + break; > > + default: > > + dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n", > > + prop); > > + ret = -EINVAL; > > + break; > > + } > > + } > > + } > > If the property is not there, the type will be uninitialized and no > warning will be spit out, are you sure you want to do that? The default value from initial ourport will be used, which is UPIO_MEM. This way it is backward compatible. Best regards, Krzysztof
On Fri, Apr 03, 2020 at 01:53:13PM +0200, Krzysztof Kozlowski wrote: > On Fri, Apr 03, 2020 at 01:42:37PM +0200, Greg KH wrote: > > On Fri, Apr 03, 2020 at 08:15:10PM +0900, Hyunki Koo wrote: > > > Support 32-bit access for the TX/RX hold registers UTXH and URXH. > > > > > > This is required for some newer SoCs. > > > > > > Signed-off-by: Hyunki Koo <hyunki00.koo@samsung.com> > > > --- > > > v2: > > > line 954 : change rd_regl to rd_reg in for backward compatibility. > > > line 2031: Add init value for ourport->port.iotype to UPIO_MEM > > > v3: > > > line 2031: remove redundant init value for ourport->port.iotype > > > v4: > > > correct variable types and change misleading function name > > > --- > > > drivers/tty/serial/samsung_tty.c | 76 +++++++++++++++++++++++++++++++++------- > > > 1 file changed, 64 insertions(+), 12 deletions(-) > > > > > > diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c > > > index 73f951d65b93..bdf1d4d12cb1 100644 > > > --- a/drivers/tty/serial/samsung_tty.c > > > +++ b/drivers/tty/serial/samsung_tty.c > > > @@ -154,12 +154,47 @@ struct s3c24xx_uart_port { > > > #define portaddrl(port, reg) \ > > > ((unsigned long *)(unsigned long)((port)->membase + (reg))) > > > > > > -#define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg))) > > > +static u32 rd_reg(struct uart_port *port, u32 reg) > > > +{ > > > + switch (port->iotype) { > > > + case UPIO_MEM: > > > + return readb_relaxed(portaddr(port, reg)); > > > + case UPIO_MEM32: > > > + return readl_relaxed(portaddr(port, reg)); > > > + default: > > > + return 0; > > > + } > > > + return 0; > > > +} > > > + > > > #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) > > > > > > -#define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg)) > > > +static void wr_reg(struct uart_port *port, u32 reg, u32 val) > > > +{ > > > + switch (port->iotype) { > > > + case UPIO_MEM: > > > + writeb_relaxed(val, portaddr(port, reg)); > > > + break; > > > + case UPIO_MEM32: > > > + writel_relaxed(val, portaddr(port, reg)); > > > + break; > > > + } > > > +} > > > + > > > #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) > > > > > > +static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val) > > > +{ > > > + switch (port->iotype) { > > > + case UPIO_MEM: > > > + writeb(val, portaddr(port, reg)); > > > + break; > > > + case UPIO_MEM32: > > > + writel(val, portaddr(port, reg)); > > > + break; > > > + } > > > +} > > > > why do you have a default for the read function, but not the write > > functions? > > The default for read will never happen and it returns bogus value just > to satisfy the compiler. That's my understanding. What would you like to > do for writes()? Print error msg? No point, it should not happen because > of check in probe(). Consistancy please, either do it for all, or none, otherwise it makes no sense at all. > > > + > > > /* Byte-order aware bit setting/clearing functions. */ > > > > > > static inline void s3c24xx_set_bit(struct uart_port *port, int idx, > > > @@ -714,7 +749,7 @@ static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport) > > > fifocnt--; > > > > > > uerstat = rd_regl(port, S3C2410_UERSTAT); > > > - ch = rd_regb(port, S3C2410_URXH); > > > + ch = rd_reg(port, S3C2410_URXH); > > > > > > if (port->flags & UPF_CONS_FLOW) { > > > int txe = s3c24xx_serial_txempty_nofifo(port); > > > @@ -826,7 +861,7 @@ static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) > > > } > > > > > > if (port->x_char) { > > > - wr_regb(port, S3C2410_UTXH, port->x_char); > > > + wr_reg(port, S3C2410_UTXH, port->x_char); > > > port->icount.tx++; > > > port->x_char = 0; > > > goto out; > > > @@ -852,7 +887,7 @@ static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) > > > if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) > > > break; > > > > > > - wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]); > > > + wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]); > > > xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); > > > port->icount.tx++; > > > count--; > > > @@ -916,7 +951,7 @@ static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) > > > /* no modem control lines */ > > > static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) > > > { > > > - unsigned int umstat = rd_regb(port, S3C2410_UMSTAT); > > > + unsigned int umstat = rd_reg(port, S3C2410_UMSTAT); > > > > > > if (umstat & S3C2410_UMSTAT_CTS) > > > return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; > > > @@ -1974,7 +2009,7 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) > > > struct device_node *np = pdev->dev.of_node; > > > struct s3c24xx_uart_port *ourport; > > > int index = probe_index; > > > - int ret; > > > + int ret, prop = 0; > > > > > > if (np) { > > > ret = of_alias_get_id(np, "serial"); > > > @@ -2000,10 +2035,27 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) > > > dev_get_platdata(&pdev->dev) : > > > ourport->drv_data->def_cfg; > > > > > > - if (np) > > > + if (np) { > > > of_property_read_u32(np, > > > "samsung,uart-fifosize", &ourport->port.fifosize); > > > > > > + if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { > > > + switch (prop) { > > > + case 1: > > > + ourport->port.iotype = UPIO_MEM; > > > + break; > > > + case 4: > > > + ourport->port.iotype = UPIO_MEM32; > > > + break; > > > + default: > > > + dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n", > > > + prop); > > > + ret = -EINVAL; > > > + break; > > > + } > > > + } > > > + } > > > > If the property is not there, the type will be uninitialized and no > > warning will be spit out, are you sure you want to do that? > > The default value from initial ourport will be used, which is UPIO_MEM. > This way it is backward compatible. Where is iotype set to UPIO_MEM as a default? thanks, greg k-h
On Fri, Apr 03, 2020 at 08:15:10PM +0900, Hyunki Koo wrote: > Support 32-bit access for the TX/RX hold registers UTXH and URXH. > > This is required for some newer SoCs. > > Signed-off-by: Hyunki Koo <hyunki00.koo@samsung.com> > --- > v2: > line 954 : change rd_regl to rd_reg in for backward compatibility. I did not see any change around line 954 in v1... so what was it? Rest looks good for me, although you should address Greg's comments. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Tested on Odroid HC1 (Exynos5422): Tested-by: Krzysztof Kozlowski <krzk@kernel.org> Best regards, Krzysztof
On Fri, Apr 03, 2020 at 01:57:15PM +0200, Greg KH wrote: > > > If the property is not there, the type will be uninitialized and no > > > warning will be spit out, are you sure you want to do that? > > > > The default value from initial ourport will be used, which is UPIO_MEM. > > This way it is backward compatible. > > Where is iotype set to UPIO_MEM as a default? Here: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/tty/serial/samsung_tty.c?h=v5.6#n1626 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/tty/serial/samsung_tty.c?h=v5.6#n1989 Best regards, Krzysztof
On Fri, Apr 03, 2020 at 08:15:10PM +0900, Hyunki Koo wrote: > Support 32-bit access for the TX/RX hold registers UTXH and URXH. > > This is required for some newer SoCs. > > Signed-off-by: Hyunki Koo <hyunki00.koo@samsung.com> > --- > v2: > line 954 : change rd_regl to rd_reg in for backward compatibility. > line 2031: Add init value for ourport->port.iotype to UPIO_MEM > v3: > line 2031: remove redundant init value for ourport->port.iotype > v4: > correct variable types and change misleading function name > --- > drivers/tty/serial/samsung_tty.c | 76 +++++++++++++++++++++++++++++++++------- > 1 file changed, 64 insertions(+), 12 deletions(-) > > diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c > index 73f951d65b93..bdf1d4d12cb1 100644 > --- a/drivers/tty/serial/samsung_tty.c > +++ b/drivers/tty/serial/samsung_tty.c > @@ -154,12 +154,47 @@ struct s3c24xx_uart_port { > #define portaddrl(port, reg) \ > ((unsigned long *)(unsigned long)((port)->membase + (reg))) > > -#define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg))) > +static u32 rd_reg(struct uart_port *port, u32 reg) > +{ > + switch (port->iotype) { > + case UPIO_MEM: > + return readb_relaxed(portaddr(port, reg)); > + case UPIO_MEM32: > + return readl_relaxed(portaddr(port, reg)); > + default: > + return 0; > + } > + return 0; > +} > + > #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) > > -#define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg)) > +static void wr_reg(struct uart_port *port, u32 reg, u32 val) > +{ > + switch (port->iotype) { > + case UPIO_MEM: > + writeb_relaxed(val, portaddr(port, reg)); > + break; > + case UPIO_MEM32: > + writel_relaxed(val, portaddr(port, reg)); > + break; > + } > +} > + > #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) > > +static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val) > +{ > + switch (port->iotype) { > + case UPIO_MEM: > + writeb(val, portaddr(port, reg)); > + break; > + case UPIO_MEM32: > + writel(val, portaddr(port, reg)); > + break; > + } > +} > + > /* Byte-order aware bit setting/clearing functions. */ > > static inline void s3c24xx_set_bit(struct uart_port *port, int idx, > @@ -714,7 +749,7 @@ static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport) > fifocnt--; > > uerstat = rd_regl(port, S3C2410_UERSTAT); > - ch = rd_regb(port, S3C2410_URXH); > + ch = rd_reg(port, S3C2410_URXH); > > if (port->flags & UPF_CONS_FLOW) { > int txe = s3c24xx_serial_txempty_nofifo(port); > @@ -826,7 +861,7 @@ static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) > } > > if (port->x_char) { > - wr_regb(port, S3C2410_UTXH, port->x_char); > + wr_reg(port, S3C2410_UTXH, port->x_char); > port->icount.tx++; > port->x_char = 0; > goto out; > @@ -852,7 +887,7 @@ static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) > if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) > break; > > - wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]); > + wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]); > xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); > port->icount.tx++; > count--; > @@ -916,7 +951,7 @@ static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) > /* no modem control lines */ > static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) > { > - unsigned int umstat = rd_regb(port, S3C2410_UMSTAT); > + unsigned int umstat = rd_reg(port, S3C2410_UMSTAT); > > if (umstat & S3C2410_UMSTAT_CTS) > return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; > @@ -1974,7 +2009,7 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) > struct device_node *np = pdev->dev.of_node; > struct s3c24xx_uart_port *ourport; > int index = probe_index; > - int ret; > + int ret, prop = 0; > > if (np) { > ret = of_alias_get_id(np, "serial"); > @@ -2000,10 +2035,27 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) > dev_get_platdata(&pdev->dev) : > ourport->drv_data->def_cfg; > > - if (np) > + if (np) { > of_property_read_u32(np, > "samsung,uart-fifosize", &ourport->port.fifosize); > > + if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { I got more thoughts... where is the binding for it? It looked like standard DT property but it is not described in device tree spec. Also, where is the user (DTS) with it? I expect such changes go with the user itself... otherwise, next cleanup it will go away. Best regards, Krzysztof
On Fri, Apr 03, 2020 at 9:00: 10PM +0900, Krzysztof Kozlowski wrote: > On Fri, Apr 03, 2020 at 08:15:10PM +0900, Hyunki Koo wrote: > > Support 32-bit access for the TX/RX hold registers UTXH and URXH. > > > > This is required for some newer SoCs. > > > > Signed-off-by: Hyunki Koo <hyunki00.koo@samsung.com> > > --- > > v2: > > line 954 : change rd_regl to rd_reg in for backward compatibility. > > I did not see any change around line 954 in v1... so what was it? 954 line is changed like below. V1 : rd_regb --> rd_regl : we thought, this register need to change to V2: rd_regl --> rd_reg : we discuss internally, and I decided not to change to existing devices for backward compatibility. So we changed to rd_reg. > > Rest looks good for me, although you should address Greg's comments. > > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Tested on Odroid > HC1 (Exynos5422): > Tested-by: Krzysztof Kozlowski <krzk@kernel.org> > > Best regards, > Krzysztof
On Fri, Apr 03, 2020 at 10:35:10PM +0900, Krzysztof Kozlowski wrote: > On Fri, Apr 03, 2020 at 08:15:10PM +0900, Hyunki Koo wrote: > > Support 32-bit access for the TX/RX hold registers UTXH and URXH. > > > > This is required for some newer SoCs. > > > > Signed-off-by: Hyunki Koo <hyunki00.koo@samsung.com> > > --- > > v2: > > line 954 : change rd_regl to rd_reg in for backward compatibility. > > line 2031: Add init value for ourport->port.iotype to UPIO_MEM > > v3: > > line 2031: remove redundant init value for ourport->port.iotype > > v4: > > correct variable types and change misleading function name > > --- > > drivers/tty/serial/samsung_tty.c | 76 > > +++++++++++++++++++++++++++++++++------- > > 1 file changed, 64 insertions(+), 12 deletions(-) > > > > diff --git a/drivers/tty/serial/samsung_tty.c > > b/drivers/tty/serial/samsung_tty.c > > index 73f951d65b93..bdf1d4d12cb1 100644 > > --- a/drivers/tty/serial/samsung_tty.c > > +++ b/drivers/tty/serial/samsung_tty.c > > @@ -154,12 +154,47 @@ struct s3c24xx_uart_port { #define > > portaddrl(port, reg) \ > > ((unsigned long *)(unsigned long)((port)->membase + (reg))) > > > > -#define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg))) > > +static u32 rd_reg(struct uart_port *port, u32 reg) { > > + switch (port->iotype) { > > + case UPIO_MEM: > > + return readb_relaxed(portaddr(port, reg)); > > + case UPIO_MEM32: > > + return readl_relaxed(portaddr(port, reg)); > > + default: > > + return 0; > > + } > > + return 0; > > +} > > + > > #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) > > > > -#define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, > > reg)) > > +static void wr_reg(struct uart_port *port, u32 reg, u32 val) { > > + switch (port->iotype) { > > + case UPIO_MEM: > > + writeb_relaxed(val, portaddr(port, reg)); > > + break; > > + case UPIO_MEM32: > > + writel_relaxed(val, portaddr(port, reg)); > > + break; > > + } > > +} > > + > > #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, > > reg)) > > > > +static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val) > > +{ > > + switch (port->iotype) { > > + case UPIO_MEM: > > + writeb(val, portaddr(port, reg)); > > + break; > > + case UPIO_MEM32: > > + writel(val, portaddr(port, reg)); > > + break; > > + } > > +} > > + > > /* Byte-order aware bit setting/clearing functions. */ > > > > static inline void s3c24xx_set_bit(struct uart_port *port, int idx, > > @@ -714,7 +749,7 @@ static void s3c24xx_serial_rx_drain_fifo(struct > s3c24xx_uart_port *ourport) > > fifocnt--; > > > > uerstat = rd_regl(port, S3C2410_UERSTAT); > > - ch = rd_regb(port, S3C2410_URXH); > > + ch = rd_reg(port, S3C2410_URXH); > > > > if (port->flags & UPF_CONS_FLOW) { > > int txe = s3c24xx_serial_txempty_nofifo(port); > > @@ -826,7 +861,7 @@ static irqreturn_t s3c24xx_serial_tx_chars(int > irq, void *id) > > } > > > > if (port->x_char) { > > - wr_regb(port, S3C2410_UTXH, port->x_char); > > + wr_reg(port, S3C2410_UTXH, port->x_char); > > port->icount.tx++; > > port->x_char = 0; > > goto out; > > @@ -852,7 +887,7 @@ static irqreturn_t s3c24xx_serial_tx_chars(int > irq, void *id) > > if (rd_regl(port, S3C2410_UFSTAT) & ourport->info- > >tx_fifofull) > > break; > > > > - wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]); > > + wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]); > > xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); > > port->icount.tx++; > > count--; > > @@ -916,7 +951,7 @@ static unsigned int > s3c24xx_serial_tx_empty(struct > > uart_port *port) > > /* no modem control lines */ > > static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) > > { > > - unsigned int umstat = rd_regb(port, S3C2410_UMSTAT); > > + unsigned int umstat = rd_reg(port, S3C2410_UMSTAT); > > > > if (umstat & S3C2410_UMSTAT_CTS) > > return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; @@ - > 1974,7 +2009,7 @@ > > static int s3c24xx_serial_probe(struct platform_device *pdev) > > struct device_node *np = pdev->dev.of_node; > > struct s3c24xx_uart_port *ourport; > > int index = probe_index; > > - int ret; > > + int ret, prop = 0; > > > > if (np) { > > ret = of_alias_get_id(np, "serial"); @@ -2000,10 > +2035,27 @@ static > > int s3c24xx_serial_probe(struct platform_device *pdev) > > dev_get_platdata(&pdev->dev) : > > ourport->drv_data->def_cfg; > > > > - if (np) > > + if (np) { > > of_property_read_u32(np, > > "samsung,uart-fifosize", &ourport->port.fifosize); > > > > + if (of_property_read_u32(np, "reg-io-width", &prop) == > 0) { > > I got more thoughts... where is the binding for it? It looked like standard > DT property but it is not described in device tree spec. > > Also, where is the user (DTS) with it? I expect such changes go with the > user itself... otherwise, next cleanup it will go away. > > Best regards, > Krzysztof Do you think this kind of change is needed? Do I have to make as a series patches with previous patch? diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index 9d2ce347875b..a57b1233c691 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -29,6 +29,14 @@ properties: reg: maxItems: 1 + reg-io-width: + description: | + The size (in bytes) of the IO accesses that should be performed + on the device. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [ 1, 4 ] +
On Mon, Apr 06, 2020 at 06:41:09AM +0900, Hyunki Koo wrote: > > > > I got more thoughts... where is the binding for it? It looked like standard > > DT property but it is not described in device tree spec. > > > > Also, where is the user (DTS) with it? I expect such changes go with the > > user itself... otherwise, next cleanup it will go away. > > > > Best regards, > > Krzysztof > > Do you think this kind of change is needed? You mean the user of this binding (DTS)? It is not required because with binding comes ABI stability. However it would be both appreciated and useful because it would clearly note that this feature is used. The feature brings additional complexity and +1 function call for each simple register access. Therefore sometime in the future, one could see it is not being used and start cleaning it up. Cleaning up usually involves looking for users, then making binding deprecated and finally removing the feature. The collaboration between the Samsung LSI and upstream is quite limited... And it basically does not exist between the Samsung mobile division and upstream. This means that when we reorganize the code, deprecate features/drivers or certain Exynos chips (e.g. 4212 and 4415 in the past) we look for users of them and if none are found - bye bye feature. The solution is either to participate (but this is difficult for mentioned Samsung divisions because of internal policies) or just add the user of such feature (e.g. DTS for evalkit). > Do I have to make as a series patches with previous patch? The DT binding you posted looks good. It should go as first patch in this series. Best regards, Krzysztof > > diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml > index 9d2ce347875b..a57b1233c691 100644 > --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml > +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml > @@ -29,6 +29,14 @@ properties: > reg: > maxItems: 1 > > + reg-io-width: > + description: | > + The size (in bytes) of the IO accesses that should be performed > + on the device. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - enum: [ 1, 4 ] > + >
On Mon, Apr 06, 2020 at 06:35:46AM +0900, Hyunki Koo wrote: > On Fri, Apr 03, 2020 at 9:00: 10PM +0900, Krzysztof Kozlowski wrote: > > On Fri, Apr 03, 2020 at 08:15:10PM +0900, Hyunki Koo wrote: > > > Support 32-bit access for the TX/RX hold registers UTXH and URXH. > > > > > > This is required for some newer SoCs. > > > > > > Signed-off-by: Hyunki Koo <hyunki00.koo@samsung.com> > > > --- > > > v2: > > > line 954 : change rd_regl to rd_reg in for backward compatibility. > > > > I did not see any change around line 954 in v1... so what was it? > 954 line is changed like below. > V1 : rd_regb --> rd_regl : we thought, this register need to change to > V2: rd_regl --> rd_reg : we discuss internally, and > I decided not to change to existing devices for backward compatibility. > So we changed to rd_reg. Thanks. Best regards, Krzysztof
diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 73f951d65b93..bdf1d4d12cb1 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -154,12 +154,47 @@ struct s3c24xx_uart_port { #define portaddrl(port, reg) \ ((unsigned long *)(unsigned long)((port)->membase + (reg))) -#define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg))) +static u32 rd_reg(struct uart_port *port, u32 reg) +{ + switch (port->iotype) { + case UPIO_MEM: + return readb_relaxed(portaddr(port, reg)); + case UPIO_MEM32: + return readl_relaxed(portaddr(port, reg)); + default: + return 0; + } + return 0; +} + #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) -#define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg)) +static void wr_reg(struct uart_port *port, u32 reg, u32 val) +{ + switch (port->iotype) { + case UPIO_MEM: + writeb_relaxed(val, portaddr(port, reg)); + break; + case UPIO_MEM32: + writel_relaxed(val, portaddr(port, reg)); + break; + } +} + #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) +static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val) +{ + switch (port->iotype) { + case UPIO_MEM: + writeb(val, portaddr(port, reg)); + break; + case UPIO_MEM32: + writel(val, portaddr(port, reg)); + break; + } +} + /* Byte-order aware bit setting/clearing functions. */ static inline void s3c24xx_set_bit(struct uart_port *port, int idx, @@ -714,7 +749,7 @@ static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport) fifocnt--; uerstat = rd_regl(port, S3C2410_UERSTAT); - ch = rd_regb(port, S3C2410_URXH); + ch = rd_reg(port, S3C2410_URXH); if (port->flags & UPF_CONS_FLOW) { int txe = s3c24xx_serial_txempty_nofifo(port); @@ -826,7 +861,7 @@ static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) } if (port->x_char) { - wr_regb(port, S3C2410_UTXH, port->x_char); + wr_reg(port, S3C2410_UTXH, port->x_char); port->icount.tx++; port->x_char = 0; goto out; @@ -852,7 +887,7 @@ static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) break; - wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]); + wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]); xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); port->icount.tx++; count--; @@ -916,7 +951,7 @@ static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) /* no modem control lines */ static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) { - unsigned int umstat = rd_regb(port, S3C2410_UMSTAT); + unsigned int umstat = rd_reg(port, S3C2410_UMSTAT); if (umstat & S3C2410_UMSTAT_CTS) return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; @@ -1974,7 +2009,7 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct s3c24xx_uart_port *ourport; int index = probe_index; - int ret; + int ret, prop = 0; if (np) { ret = of_alias_get_id(np, "serial"); @@ -2000,10 +2035,27 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) dev_get_platdata(&pdev->dev) : ourport->drv_data->def_cfg; - if (np) + if (np) { of_property_read_u32(np, "samsung,uart-fifosize", &ourport->port.fifosize); + if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { + switch (prop) { + case 1: + ourport->port.iotype = UPIO_MEM; + break; + case 4: + ourport->port.iotype = UPIO_MEM32; + break; + default: + dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n", + prop); + ret = -EINVAL; + break; + } + } + } + if (ourport->drv_data->fifosize[index]) ourport->port.fifosize = ourport->drv_data->fifosize[index]; else if (ourport->info->fifosize) @@ -2185,7 +2237,7 @@ static int s3c24xx_serial_get_poll_char(struct uart_port *port) if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) return NO_POLL_CHAR; - return rd_regb(port, S3C2410_URXH); + return rd_reg(port, S3C2410_URXH); } static void s3c24xx_serial_put_poll_char(struct uart_port *port, @@ -2200,7 +2252,7 @@ static void s3c24xx_serial_put_poll_char(struct uart_port *port, while (!s3c24xx_serial_console_txrdy(port, ufcon)) cpu_relax(); - wr_regb(port, S3C2410_UTXH, c); + wr_reg(port, S3C2410_UTXH, c); } #endif /* CONFIG_CONSOLE_POLL */ @@ -2212,7 +2264,7 @@ s3c24xx_serial_console_putchar(struct uart_port *port, int ch) while (!s3c24xx_serial_console_txrdy(port, ufcon)) cpu_relax(); - wr_regb(port, S3C2410_UTXH, ch); + wr_reg(port, S3C2410_UTXH, ch); } static void @@ -2612,7 +2664,7 @@ static void samsung_early_putc(struct uart_port *port, int c) else samsung_early_busyuart(port); - writeb(c, port->membase + S3C2410_UTXH); + wr_reg_barrier(port, S3C2410_UTXH, c); } static void samsung_early_write(struct console *con, const char *s,
Support 32-bit access for the TX/RX hold registers UTXH and URXH. This is required for some newer SoCs. Signed-off-by: Hyunki Koo <hyunki00.koo@samsung.com> --- v2: line 954 : change rd_regl to rd_reg in for backward compatibility. line 2031: Add init value for ourport->port.iotype to UPIO_MEM v3: line 2031: remove redundant init value for ourport->port.iotype v4: correct variable types and change misleading function name --- drivers/tty/serial/samsung_tty.c | 76 +++++++++++++++++++++++++++++++++------- 1 file changed, 64 insertions(+), 12 deletions(-)