@@ -239,8 +239,13 @@ struct exynos_dsi_transfer {
#define DSIM_STATE_CMD_LPM BIT(2)
#define DSIM_STATE_VIDOUT_AVAILABLE BIT(3)
+enum exynos_reg_offset {
+ EXYNOS_REG_OFS,
+ EXYNOS5433_REG_OFS
+};
+
struct exynos_dsi_driver_data {
- const unsigned int *reg_ofs;
+ enum exynos_reg_offset reg_ofs;
unsigned int plltmr_reg;
unsigned int has_freqband:1;
unsigned int has_clklane_stop:1;
@@ -317,18 +322,6 @@ enum reg_idx {
NUM_REGS
};
-static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx,
- u32 val)
-{
-
- writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
-}
-
-static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx)
-{
- return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
-}
-
static const unsigned int exynos_reg_ofs[] = {
[DSIM_STATUS_REG] = 0x00,
[DSIM_SWRST_REG] = 0x04,
@@ -377,6 +370,31 @@ static const unsigned int exynos5433_reg_ofs[] = {
[DSIM_PHYTIMING2_REG] = 0xBC,
};
+static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx,
+ u32 val)
+{
+ const unsigned int *reg_ofs;
+
+ if (dsi->driver_data->reg_ofs == EXYNOS5433_REG_OFS)
+ reg_ofs = exynos5433_reg_ofs;
+ else
+ reg_ofs = exynos_reg_ofs;
+
+ writel(val, dsi->reg_base + reg_ofs[idx]);
+}
+
+static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx)
+{
+ const unsigned int *reg_ofs;
+
+ if (dsi->driver_data->reg_ofs == EXYNOS5433_REG_OFS)
+ reg_ofs = exynos5433_reg_ofs;
+ else
+ reg_ofs = exynos_reg_ofs;
+
+ return readl(dsi->reg_base + reg_ofs[idx]);
+}
+
enum reg_value_idx {
RESET_TYPE,
PLL_TIMER,
@@ -450,7 +468,7 @@ static const unsigned int exynos5433_reg_values[] = {
};
static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
- .reg_ofs = exynos_reg_ofs,
+ .reg_ofs = EXYNOS_REG_OFS,
.plltmr_reg = 0x50,
.has_freqband = 1,
.has_clklane_stop = 1,
@@ -462,7 +480,7 @@ static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
};
static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
- .reg_ofs = exynos_reg_ofs,
+ .reg_ofs = EXYNOS_REG_OFS,
.plltmr_reg = 0x50,
.has_freqband = 1,
.has_clklane_stop = 1,
@@ -474,7 +492,7 @@ static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
};
static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
- .reg_ofs = exynos_reg_ofs,
+ .reg_ofs = EXYNOS_REG_OFS,
.plltmr_reg = 0x58,
.num_clks = 2,
.max_freq = 1000,
@@ -484,7 +502,7 @@ static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
};
static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
- .reg_ofs = exynos5433_reg_ofs,
+ .reg_ofs = EXYNOS5433_REG_OFS,
.plltmr_reg = 0xa0,
.has_clklane_stop = 1,
.num_clks = 5,
@@ -495,7 +513,7 @@ static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
};
static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = {
- .reg_ofs = exynos5433_reg_ofs,
+ .reg_ofs = EXYNOS5433_REG_OFS,
.plltmr_reg = 0xa0,
.has_clklane_stop = 1,
.num_clks = 2,
Different revisions of the MIPI-DSI PHY have slightly different register layouts. Currently, the register layout was stored per platform, which makes it necessary to define the layout for each new platform. Keep the register layout in the driver and use identifiers to specify which register layout shall be used on a platform. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> --- v2: none --- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 54 ++++++++++++++++--------- 1 file changed, 36 insertions(+), 18 deletions(-)