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Fri, 23 Oct 2020 07:57:54 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jaehoon Chung , Marek Szyprowski , Jingoo Han , Krzysztof Kozlowski , Bjorn Helgaas , Lorenzo Pieralisi , Vinod Koul , Kishon Vijay Abraham I , Rob Herring Subject: [PATCH v2 2/6] dt-bindings: pci: add the samsung,exynos-pcie binding Date: Fri, 23 Oct 2020 09:57:40 +0200 Message-Id: <20201023075744.26200-3-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201023075744.26200-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrIKsWRmVeSWpSXmKPExsWy7djPc7rMvZPiDb4tkrVY0pRhMf/IOVaL G7/aWC1WfJnJbnHhaQ+bxfnzG9gtLu+aw2Zxdt5xNosZ5/cxWbz5/YLdYu2Ru+wWrXuPsFvs vHOC2YHXY828NYweO2fdZfdYsKnUY9OqTjaPvi2rGD2O39jO5PF5k1wAexSXTUpqTmZZapG+ XQJXxutPk5gKrshWzO94xdjAeFGsi5GTQ0LAROL5wW6WLkYuDiGBFYwS/R8PsEE4XxglTjXP YYRwPjNKXL++HijDAdby/pI+RHw5o8SVPzDtQB0LdhxnApnLJmAo0fW2C6xBRMBB4sdXC5Aa ZoFFzBIN/UcYQWqEBfwlvh/fCmazCKhKPNvTCNbLK2Ar8eDmHTaI++QlVm84wAxicwrYSbxr uAd2kYTAOnaJW48/MUIUuUjseL+fCcIWlnh1fAs7hC0jcXpyDwtEQzOjxMNza9khnB5GictN M6C6rSXunPsFdiqzgKbE+l36EGFHiZ3N05kgXuaTuPFWECTMDGRO2jadGSLMK9HRJgRRrSYx 6/g6uLUHL1xihrA9JC5snscCYgsJTGSUuH/QZAKj/CyEXQsYGVcxiqeWFuempxYb56WW6xUn 5haX5qXrJefnbmIEJpzT/45/3cG470/SIUYBDkYlHt6ECRPjhVgTy4orcw8xSnAwK4nwOp09 HSfEm5JYWZValB9fVJqTWnyIUZqDRUmc13jRy1ghgfTEktTs1NSC1CKYLBMHp1QD4/ZXV5Yu /bK2spbrilbD1yceKocMJqv0/ZtcLOZ0zVP1woyrvCFh0WuCH8lFPzk2KdYm8hxHwVLZ6FXd tspWHyoZA1eaG3zO7VVzec9jWFKd3bb5oWkJX27NhHCTY5s8S37vWq3vf148ds2Cbw4vDqdM DHnocGbGuQv1x1xZvL6cW5W4s9L7qBJLcUaioRZzUXEiAHmOEOA0AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpikeLIzCtJLcpLzFFi42I5/e/4XV3m3knxBo3POC2WNGVYzD9yjtXi xq82VosVX2ayW1x42sNmcf78BnaLy7vmsFmcnXeczWLG+X1MFm9+v2C3WHvkLrtF694j7BY7 75xgduD1WDNvDaPHzll32T0WbCr12LSqk82jb8sqRo/jN7YzeXzeJBfAHqVnU5RfWpKqkJFf XGKrFG1oYaRnaGmhZ2RiqWdobB5rZWSqpG9nk5Kak1mWWqRvl6CX8frTJKaCK7IV8zteMTYw XhTrYuTgkBAwkXh/Sb+LkZNDSGApo8TOdzwgtoSAjMTJaQ2sELawxJ9rXWxdjFxANZ8YJXZ8 m8cIkmATMJToeguS4OQQEXCSeD/5IjNIEbPAGmaJxrZuJpCEsICvxNkOiEksAqoSz/Y0gsV5 BWwlHty8wwaxQV5i9YYDzCA2p4CdxLuGe4wQF9lKHD50lXkCI98CRoZVjCKppcW56bnFhnrF ibnFpXnpesn5uZsYgeG/7djPzTsYL20MPsQowMGoxMObMGFivBBrYllxZe4hRgkOZiURXqez p+OEeFMSK6tSi/Lji0pzUosPMZoCHTWRWUo0OR8Ym3kl8YamhuYWlobmxubGZhZK4rwdAgdj hATSE0tSs1NTC1KLYPqYODilGhgFqj+Y7brm9DBf59/0rDX9fx3MEksWq7Ct3bhhXWrDa8WO b88ORzplFgoVpr24tuPP+WVTHKo/f9+30PDykzrdzOkLnWs2NKb9rfnPG3qO6YBbNm9MP9OB +6viTp3oMtuVWe+asVOnQ9LlhvxJq2vGly6rZTV93LwlcvlJrY0rHs97fU7qhPk6JZbijERD Leai4kQAlwoljZUCAAA= X-CMS-MailID: 20201023075755eucas1p290b7bc020e46b86fe5e7591877f87117 X-Msg-Generator: CA X-RootMTR: 20201023075755eucas1p290b7bc020e46b86fe5e7591877f87117 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20201023075755eucas1p290b7bc020e46b86fe5e7591877f87117 References: <20201023075744.26200-1-m.szyprowski@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433 variant). Based on the text dt-binding posted by Jaehoon Chung. Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski --- .../bindings/pci/samsung,exynos-pcie.yaml | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml new file mode 100644 index 000000000000..6ddba0cb400e --- /dev/null +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC series PCIe Host Controller Device Tree Bindings + +maintainers: + - Marek Szyprowski + - Jaehoon Chung + +description: |+ + Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare + PCIe IP and thus inherits all the common properties defined in + designware-pcie.txt. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: samsung,exynos5433-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: External Local Bus interface (ELBI) registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: dbi + - const: elbi + - const: config + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PCIe bridge clock + - description: PCIe bus clock + + clock-names: + items: + - const: pcie + - const: pcie_bus + + phys: + maxItems: 1 + + vdd10-supply: + description: + Phandle to a regulator that provides 1.0V power to the PCIe block. + + vdd18-supply: + description: + Phandle to a regulator that provides 1.8V power to the PCIe block. + + num-lanes: + const: 1 + +required: + - reg + - reg-names + - interrupts + - "#address-cells" + - "#size-cells" + - "#interrupt-cells" + - interrupt-map + - interrupt-map-mask + - ranges + - bus-range + - device_type + - num-lanes + - clocks + - clock-names + - phys + - vdd10-supply + - vdd18-supply + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + pcie: pcie@15700000 { + compatible = "samsung,exynos5433-pcie"; + reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>; + reg-names = "dbi", "elbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupts = ; + clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>; + clock-names = "pcie", "pcie_bus"; + phys = <&pcie_phy>; + pinctrl-0 = <&pcie_bus &pcie_wlanen>; + pinctrl-names = "default"; + num-lanes = <1>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, + <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; + vdd10-supply = <&ldo6_reg>; + vdd18-supply = <&ldo7_reg>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; + }; +...