| Message ID | 20210709065711.25195-4-chanho61.park@samsung.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | introduce exynosauto v9 ufs driver | expand |
Hi Chanho > -----Original Message----- > From: Chanho Park <chanho61.park@samsung.com> > Sent: 09 July 2021 12:27 > To: Alim Akhtar <alim.akhtar@samsung.com>; James E . J . Bottomley > <jejb@linux.ibm.com>; Martin K . Petersen <martin.petersen@oracle.com> > Cc: Can Guo <cang@codeaurora.org>; Jaegeuk Kim <jaegeuk@kernel.org>; > Kiwoong Kim <kwmad.kim@samsung.com>; Avri Altman > <avri.altman@wdc.com>; Adrian Hunter <adrian.hunter@intel.com>; > Christoph Hellwig <hch@infradead.org>; Bart Van Assche > <bvanassche@acm.org>; jongmin jeong <jjmin.jeong@samsung.com>; > Gyunghoon Kwon <goodjob.kwon@samsung.com>; linux-samsung- > soc@vger.kernel.org; linux-scsi@vger.kernel.org; Chanho Park > <chanho61.park@samsung.com> > Subject: [PATCH 03/15] scsi: ufs: ufs-exynos: change pclk available max value > > To support 167MHz PCLK, we need to adjust the maximum value. > > Signed-off-by: Chanho Park <chanho61.park@samsung.com> > --- Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> > drivers/scsi/ufs/ufs-exynos.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h > index 67505fe32ebf..475a5adf0f8b 100644 > --- a/drivers/scsi/ufs/ufs-exynos.h > +++ b/drivers/scsi/ufs/ufs-exynos.h > @@ -99,7 +99,7 @@ struct exynos_ufs; > #define PA_HIBERN8TIME_VAL 0x20 > > #define PCLK_AVAIL_MIN 70000000 > -#define PCLK_AVAIL_MAX 133000000 > +#define PCLK_AVAIL_MAX 167000000 > > struct exynos_ufs_uic_attr { > /* TX Attributes */ > -- > 2.32.0
diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h index 67505fe32ebf..475a5adf0f8b 100644 --- a/drivers/scsi/ufs/ufs-exynos.h +++ b/drivers/scsi/ufs/ufs-exynos.h @@ -99,7 +99,7 @@ struct exynos_ufs; #define PA_HIBERN8TIME_VAL 0x20 #define PCLK_AVAIL_MIN 70000000 -#define PCLK_AVAIL_MAX 133000000 +#define PCLK_AVAIL_MAX 167000000 struct exynos_ufs_uic_attr { /* TX Attributes */
To support 167MHz PCLK, we need to adjust the maximum value. Signed-off-by: Chanho Park <chanho61.park@samsung.com> --- drivers/scsi/ufs/ufs-exynos.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)