Message ID | 20211007080934.108804-8-chanho61.park@samsung.com (mailing list archive) |
---|---|
State | Not Applicable |
Headers | show |
Series | introduce exynosauto v9 ufs driver | expand |
> > PA_PWRMODEUSERDATA0 -> DL_FC0PROTTIMEOUTVAL > PA_PWRMODEUSERDATA1 -> DL_TC0REPLAYTIMEOUTVAL > PA_PWRMODEUSERDATA2 -> DL_AFC0REQTIMEOUTVAL Is there a specific reason why this fix is part of the exynosauto series? Thanks, Avri
Hi, Thanks for your review. > -----Original Message----- > From: Avri Altman <Avri.Altman@wdc.com> > Sent: Thursday, October 14, 2021 9:12 PM > To: Chanho Park <chanho61.park@samsung.com>; Alim Akhtar > <alim.akhtar@samsung.com>; James E . J . Bottomley <jejb@linux.ibm.com>; > Martin K . Petersen <martin.petersen@oracle.com>; Krzysztof Kozlowski > <krzysztof.kozlowski@canonical.com> > Cc: Bean Huo <beanhuo@micron.com>; Bart Van Assche <bvanassche@acm.org>; > Adrian Hunter <adrian.hunter@intel.com>; hch@infradead.org; Can Guo > <cang@codeaurora.org>; Jaegeuk Kim <jaegeuk@kernel.org>; Jaehoon Chung > <jh80.chung@samsung.com>; Gyunghoon Kwon <goodjob.kwon@samsung.com>; Sowon > Na <sowon.na@samsung.com>; linux-samsung-soc@vger.kernel.org; linux- > scsi@vger.kernel.org; Kiwoong Kim <kwmad.kim@samsung.com> > Subject: RE: [PATCH v4 07/16] scsi: ufs: ufs-exynos: correct timeout value > setting registers > > > > > PA_PWRMODEUSERDATA0 -> DL_FC0PROTTIMEOUTVAL > > PA_PWRMODEUSERDATA1 -> DL_TC0REPLAYTIMEOUTVAL > > PA_PWRMODEUSERDATA2 -> DL_AFC0REQTIMEOUTVAL > Is there a specific reason why this fix is part of the exynosauto series? I found the issue when I made the patches with some refactoring of ufs-exynos driver. I can send it separately. Best Regards, Chanho Park
diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c index e800fb9e1ce4..41797f499544 100644 --- a/drivers/scsi/ufs/ufs-exynos.c +++ b/drivers/scsi/ufs/ufs-exynos.c @@ -643,9 +643,9 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba, } /* setting for three timeout values for traffic class #0 */ - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 8064); - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 28224); - ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 20160); + ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064); + ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224); + ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160); return 0; out: