From patchwork Thu Dec 9 20:54:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?M=C3=A5rten_Lindahl?= X-Patchwork-Id: 12668283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42803C433F5 for ; Thu, 9 Dec 2021 20:59:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232177AbhLIVCe (ORCPT ); Thu, 9 Dec 2021 16:02:34 -0500 Received: from smtp2.axis.com ([195.60.68.18]:28277 "EHLO smtp2.axis.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229505AbhLIVCe (ORCPT ); Thu, 9 Dec 2021 16:02:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=axis.com; q=dns/txt; s=axis-central1; t=1639083540; x=1670619540; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QmD3AuY/nFM7k+lgLyZOUw4foDKoYXZZ/7XSpW0mJrM=; b=VhuE9x8IEFxqAce6yvuxridl8YsxRCGpMSRUsHbtL6vufm5y6IPE3YiL hG6Uue01FIg/0htCEjP5FnV3qVmip4CXq6OJgIZ+m22RWbKyfRSNSTnUb I7gDRwrO1+cjVyMpwj0jtVayRthQ6vnIfT7HOR/iMUBIJygjvGBZ23GCm WbuaIeUDBMMxwgLTT2wbZEEM9WJSjI0DiT9bo/8oYpuDaWHiRuUERCqs0 U5rbV6obqH4vUOcSSsTuxN5VOLAHOWhdkn1GIF+9IkLKvucsdvMPP7jbN x3U54dLQ1+kzCTJFR8Ei1QpqIV+zl731cjtLemZi0OdUDBAaLvszvRtra A==; From: =?utf-8?q?M=C3=A5rten_Lindahl?= To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Jaehoon Chung CC: Doug Anderson , , , , , , =?utf-8?q?M=C3=A5rten_Lindahl?= Subject: [PATCH v4 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8 Date: Thu, 9 Dec 2021 21:54:53 +0100 Message-ID: <20211209205456.11027-2-marten.lindahl@axis.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20211209205456.11027-1-marten.lindahl@axis.com> References: <20211209205456.11027-1-marten.lindahl@axis.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The ARTPEC-8 SoC has a DWMMC controller that is compatible with the Exynos 7 version v2.70a. The main differences from Exynos 7 is that it does not support HS400 and has extended data read timeout. Add compatibility string "axis,artpec8-dw-mshc" for ARTPEC-8. Signed-off-by: Mårten Lindahl Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring --- v2: - Change compatible string vendor prefix v3 -> v4: - Add Krzysztof's Reviewed-by tag Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index 0419a63f73a0..753e9d7d8956 100644 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt @@ -22,6 +22,8 @@ Required Properties: specific extensions. - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7 specific extensions having an SMU. + - "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific + extensions. * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface unit (ciu) clock. This property is applicable only for Exynos5 SoC's and