| Message ID | 20220129193646.372481-1-krzysztof.kozlowski@canonical.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | a0d5455330ece6f50ddf9e71d530f91c302803e9 |
| Headers | show |
| Series | [1/8] arm64: dts: exynos: adjust USB DRD clocks with dtschema in Exynos7 | expand |
On Sat, 29 Jan 2022 20:36:39 +0100, Krzysztof Kozlowski wrote: > Use the same order of USB 3.0 DRD controller clocks as in Exynos5433. > > Applied, thanks! [1/8] arm64: dts: exynos: adjust USB DRD clocks with dtschema in Exynos7 commit: a0d5455330ece6f50ddf9e71d530f91c302803e9 Best regards,
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 3364b09c3158..e38bb02a2152 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -684,11 +684,10 @@ usbdrd_phy: phy@15500000 { reg = <0x15500000 0x100>; clocks = <&clock_fsys0 ACLK_USBDRD300>, <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, - <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, + <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, <&clock_fsys0 SCLK_USBDRD300_REFCLK>; - clock-names = "phy", "ref", "phy_pipe", - "phy_utmi", "itp"; + clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp"; samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <1>; };
Use the same order of USB 3.0 DRD controller clocks as in Exynos5433. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> --- arch/arm64/boot/dts/exynos/exynos7.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)