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Sun, 22 May 2022 18:54:24 +0900 (KST) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20220520145802epcas5p2153cb572493e3bccd702e0ecce1171fb~w2Bz5l2F30456204562epcas5p28; Fri, 20 May 2022 14:58:02 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20220520145802epsmtrp2baba019b24fd22c46067f5de9a8549f1~w2Bz4pZNy0678606786epsmtrp2K; Fri, 20 May 2022 14:58:02 +0000 (GMT) X-AuditID: b6c32a4a-b51ff70000002663-f2-628a08504f10 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 66.E2.11276.97CA7826; Fri, 20 May 2022 23:58:02 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220520145800epsmtip1336ebd9f9cb40b177ac85b01ce6e1a7c~w2Bx2w8wv1422614226epsmtip1_; Fri, 20 May 2022 14:57:59 +0000 (GMT) From: Tamseel Shams To: jic23@kernel.org, lars@metafoo.de, robh+dt@kernel.org, krzk+dt@kernel.org Cc: geert@linux-m68k.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, alim.akhtar@samsung.com, paul@crapouillou.net, linux-fsd@tesla.com, Tamseel Shams Subject: [PATCH v2 2/3] iio: adc: exynos-adc: Add support for ADC FSD-HW controller Date: Fri, 20 May 2022 20:28:19 +0530 Message-Id: <20220520145820.67667-3-m.shams@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220520145820.67667-1-m.shams@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjk+LIzCtJLcpLzFFi42LZdlhTUzeAoyvJ4F+DnMWDedvYLOYfOcdq 8ezWXiaLB02rmCxezrrHZrFk8nxWi02Pr7FaPHwVbjHvyDsWi8u75rBZzDi/j8nibutidov+ xZdYLFr3HmF34PNYfamdzWPTqk42j0OHOxg9Ni+p91jy5hCrR9+WVYwe/5rmsnt83iQXwBGV bZORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtqq+TiE6DrlpkDdLaSQlli TilQKCCxuFhJ386mKL+0JFUhI7+4xFYptSAlp8CkQK84Mbe4NC9dLy+1xMrQwMDIFKgwITvj 4NUzLAXv5CouXdRqYHwi2cXIwSEhYCIxbbZAFyMXh5DAbkaJ1fsmMEE4nxglZv3cwQzhfGOU WHH6BVsXIydYx5kLt1khEnsZJVq3rIZqaWGS2HvkMDvIXDYBTYnj57lBTBEBf4nOvy4gJcwC y5kkTq+bBjZIWCBUov/VfTCbRUBV4vrtXcwgNq+AhcTas1+hlslLrN5wACzOKWAp8fVnEyPI IAmBXg6JmZPmsUIUuUjc//aKEcIWlnh1fAs7hC0l8fndXqhB6RJzH/YyQdgFEst2fYeqsZc4 cGUOC8ihzEA3r9+lDxGWlZh6ah1YObMAn0Tv7ydQrbwSO+bB2IoS/3f3Q40Rl3i3YgrUOR4S bRsPMkLCpIdRYs7rX6wTGOVmIaxYwMi4ilEytaA4Nz212LTAKC+1HB5nyfm5mxjBCVPLawfj wwcf9A4xMnEwHmKU4GBWEuHdntiRJMSbklhZlVqUH19UmpNafIjRFBiAE5mlRJPzgSk7ryTe 0MTSwMTMzMzE0tjMUEmcV+B/Y5KQQHpiSWp2ampBahFMHxMHp1QD0+YLi6byBC8XznuRZXNr QbdkcneGcl/bpHL1Ll7/Tw3TzWf4sDK9Ovr9hLHRm4yChNMSC4TZTwqbJs68yTL1ZHrkgXRn s4x7179w1/x54Mz78YaHAZt24s9zxr9mypmF2D+8fDg+fBdb0DpzyX0nb7yNO/NzSYxjuacy 7xano2sFZdM2msgWhM7eYrlLf02iBQf3JpEwQQ5WHuFtT67r71on/Xa67+9vlvnJOVzbez7o X5n0y757f+L3dexev5jslz/yXWLjV3AweuMxESPVWX8bPn4t0t177JHde3n+0D+dnJ6ur7zL ZgcHHOyquHhj9YvSqvD5L9j9VETPqFi8cGteslv5x+yPOtbWeeUqSizFGYmGWsxFxYkANLiA TyEEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrGLMWRmVeSWpSXmKPExsWy7bCSnG7VmvYkg5l/GS0ezNvGZjH/yDlW i2e39jJZPGhaxWTxctY9Noslk+ezWmx6fI3V4uGrcIt5R96xWFzeNYfNYsb5fUwWd1sXs1v0 L77EYtG69wi7A5/H6kvtbB6bVnWyeRw63MHosXlJvceSN4dYPfq2rGL0+Nc0l93j8ya5AI4o LpuU1JzMstQifbsEroyDV8+wFLyTq7h0UauB8YlkFyMnh4SAicSZC7dZuxi5OIQEdjNKzOia wwKREJeY9ms/I4QtLLHy33N2iKImJol1f9+xdTFycLAJaEocP88NUiMiECyx+NBhZpAaZoGN TBL/d3exgiSEgRKzbk9iBrFZBFQlrt/eBWbzClhIrD37lQ1igbzE6g0HwOKcApYSX382gS0W AqpZ0fiNeQIj3wJGhlWMkqkFxbnpucWGBYZ5qeV6xYm5xaV56XrJ+bmbGMFBraW5g3H7qg96 hxiZOBgPMUpwMCuJ8DLmtiQJ8aYkVlalFuXHF5XmpBYfYpTmYFES573QdTJeSCA9sSQ1OzW1 ILUIJsvEwSnVwLRf88WKyQflwtctPni9+KT2+1+cGdELIpiaZ2W1MXosOfP0/6PYy1xTTFwi LUR3HK404Hq5yU+qO7AmsbFow4kQiVLF0k3fL3X9jeGeUMGauu2+uIh8cGnoz4XeOb4z+Mpv xCSu33W5pDpLRX5Zo09csMOmD3ozXS+KpTb8PKN07O3Mtwk2RdfucW5olLUxaHuX7FF8wl11 +684Y7P3fx5MK/DPinMP4Nsb9jCUaXuGj/Lf5Ys7Kpwu6Gj6p/mlZDmsaVq+an93ojU//8uV oo1Hct9J1ockLWtcqcYVqcaVHvi52sPg3OnNH6ZwJd1y2R3e1Xivvn7fnSUHpWxD52szG+7s 9Pv55pR49ZNuJZbijERDLeai4kQAHlqIidkCAAA= X-CMS-MailID: 20220520145802epcas5p2153cb572493e3bccd702e0ecce1171fb X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220520145802epcas5p2153cb572493e3bccd702e0ecce1171fb References: <20220520145820.67667-1-m.shams@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Alim Akhtar Exynos's ADC-FSD-HW has some difference in registers set, number of programmable channels (16 channel) etc. This patch adds support for ADC-FSD-HW controller version. Signed-off-by: Alim Akhtar Signed-off-by: Tamseel Shams Reviewed-by: Krzysztof Kozlowski --- - Changes since v1 * Addressed Jonathan's comment by using already provided isr handle drivers/iio/adc/exynos_adc.c | 55 ++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c index cff1ba57fb16..183ae591327a 100644 --- a/drivers/iio/adc/exynos_adc.c +++ b/drivers/iio/adc/exynos_adc.c @@ -55,6 +55,11 @@ #define ADC_V2_INT_ST(x) ((x) + 0x14) #define ADC_V2_VER(x) ((x) + 0x20) +/* ADC_FSD_HW register definitions */ +#define ADC_FSD_DAT(x) ((x) + 0x08) +#define ADC_FSD_DAT_SUM(x) ((x) + 0x0C) +#define ADC_FSD_DBG_DATA(x) ((x) + 0x1C) + /* Bit definitions for ADC_V1 */ #define ADC_V1_CON_RES (1u << 16) #define ADC_V1_CON_PRSCEN (1u << 14) @@ -92,6 +97,7 @@ /* Bit definitions for ADC_V2 */ #define ADC_V2_CON1_SOFT_RESET (1u << 2) +#define ADC_V2_CON1_SOFT_NON_RESET (1u << 1) #define ADC_V2_CON2_OSEL (1u << 10) #define ADC_V2_CON2_ESEL (1u << 9) @@ -100,6 +106,7 @@ #define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0) #define ADC_V2_CON2_ACH_MASK 0xF +#define MAX_ADC_FSD_CHANNELS 16 #define MAX_ADC_V2_CHANNELS 10 #define MAX_ADC_V1_CHANNELS 8 #define MAX_EXYNOS3250_ADC_CHANNELS 2 @@ -484,6 +491,43 @@ static const struct exynos_adc_data exynos7_adc_data = { .start_conv = exynos_adc_v2_start_conv, }; +static void exynos_adc_fsd_init_hw(struct exynos_adc *info) +{ + u32 con2; + + writel(ADC_V2_CON1_SOFT_RESET, ADC_V2_CON1(info->regs)); + + writel(ADC_V2_CON1_SOFT_NON_RESET, ADC_V2_CON1(info->regs)); + + con2 = ADC_V2_CON2_C_TIME(6); + writel(con2, ADC_V2_CON2(info->regs)); + + /* Enable interrupts */ + writel(1, ADC_V2_INT_EN(info->regs)); +} + +static void exynos_adc_fsd_exit_hw(struct exynos_adc *info) +{ + u32 con2; + + con2 = readl(ADC_V2_CON2(info->regs)); + con2 &= ~ADC_V2_CON2_C_TIME(7); + writel(con2, ADC_V2_CON2(info->regs)); + + /* Disable interrupts */ + writel(0, ADC_V2_INT_EN(info->regs)); +} + +static const struct exynos_adc_data fsd_hw_adc_data = { + .num_channels = MAX_ADC_FSD_CHANNELS, + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ + + .init_hw = exynos_adc_fsd_init_hw, + .exit_hw = exynos_adc_fsd_exit_hw, + .clear_irq = exynos_adc_v2_clear_irq, + .start_conv = exynos_adc_v2_start_conv, +}; + static const struct of_device_id exynos_adc_match[] = { { .compatible = "samsung,s3c2410-adc", @@ -518,6 +562,9 @@ static const struct of_device_id exynos_adc_match[] = { }, { .compatible = "samsung,exynos7-adc", .data = &exynos7_adc_data, + }, { + .compatible = "samsung,exynos-adc-fsd-hw", + .data = &fsd_hw_adc_data, }, {}, }; @@ -626,6 +673,8 @@ static irqreturn_t exynos_adc_isr(int irq, void *dev_id) info->ts_x = readl(ADC_V1_DATX(info->regs)); info->ts_y = readl(ADC_V1_DATY(info->regs)); writel(ADC_TSC_WAIT4INT | ADC_S3C2443_TSC_UD_SEN, ADC_V1_TSC(info->regs)); + } else if (of_device_is_compatible(info->dev->of_node, "samsung,exynos-adc-fsd-hw")) { + info->value = readl(ADC_FSD_DAT(info->regs)) & mask; } else { info->value = readl(ADC_V1_DATX(info->regs)) & mask; } @@ -719,6 +768,12 @@ static const struct iio_chan_spec exynos_adc_iio_channels[] = { ADC_CHANNEL(7, "adc7"), ADC_CHANNEL(8, "adc8"), ADC_CHANNEL(9, "adc9"), + ADC_CHANNEL(10, "adc10"), + ADC_CHANNEL(11, "adc11"), + ADC_CHANNEL(12, "adc12"), + ADC_CHANNEL(13, "adc13"), + ADC_CHANNEL(14, "adc14"), + ADC_CHANNEL(15, "adc15"), }; static int exynos_adc_remove_devices(struct device *dev, void *c)