diff mbox series

[v2,7/7] iommu/exynos: Enable default VM instance on SysMMU v7

Message ID 20220710230603.13526-8-semen.protsenko@linaro.org (mailing list archive)
State Not Applicable
Headers show
Series iommu/exynos: Add basic support for SysMMU v7 | expand

Commit Message

Sam Protsenko July 10, 2022, 11:06 p.m. UTC 
In order to enable SysMMU v7 with VM register layout, at least the
default VM instance (n=0) must be enabled, in addition to enabling the
SysMMU itself. To do so, add corresponding write to MMU_CTRL_VM[0]
register, before writing to MMU_CTRL register.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
---
Changes in v2:
  - Extracted VM enabling code to the separate function
  - Used new SysMMU read/write functions to access the registers

 drivers/iommu/exynos-iommu.c | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

Comments

Marek Szyprowski July 12, 2022, 3:53 p.m. UTC | #1 
On 11.07.2022 01:06, Sam Protsenko wrote:
> In order to enable SysMMU v7 with VM register layout, at least the
> default VM instance (n=0) must be enabled, in addition to enabling the
> SysMMU itself. To do so, add corresponding write to MMU_CTRL_VM[0]
> register, before writing to MMU_CTRL register.
>
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> Changes in v2:
>    - Extracted VM enabling code to the separate function
>    - Used new SysMMU read/write functions to access the registers
>
>   drivers/iommu/exynos-iommu.c | 24 ++++++++++++++++++++----
>   1 file changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
> index 64bf3331064f..2b333e137f57 100644
> --- a/drivers/iommu/exynos-iommu.c
> +++ b/drivers/iommu/exynos-iommu.c
> @@ -135,6 +135,8 @@ static u32 lv2ent_offset(sysmmu_iova_t iova)
>   #define CFG_SYSSEL	(1 << 22) /* System MMU 3.2 only */
>   #define CFG_FLPDCACHE	(1 << 20) /* System MMU 3.2+ only */
>   
> +#define CTRL_VM_ENABLE			BIT(0)
> +#define CTRL_VM_FAULT_MODE_STALL	BIT(3)
>   #define CAPA0_CAPA1_EXIST		BIT(11)
>   #define CAPA1_VCR_ENABLED		BIT(14)
>   
> @@ -183,6 +185,7 @@ enum {
>   	IDX_FLUSH_END,
>   	IDX_INT_STATUS,
>   	IDX_INT_CLEAR,
> +	IDX_CTRL_VM,
>   	MAX_REG_IDX
>   };
>   
> @@ -196,22 +199,22 @@ static const unsigned int sysmmu_regs[MAX_REG_SET][MAX_REG_IDX] = {
>   	/* SysMMU v1..v3 */
>   	{
>   		0x00, 0x04, 0x08, 0x14, 0x0c, 0x10, 0x1, 0x1, 0x1,
> -		0x18, 0x1c,
> +		0x18, 0x1c, 0x1,
>   	},
>   	/* SysMMU v5 */
>   	{
>   		0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x20, 0x24,
> -		0x60, 0x64,
> +		0x60, 0x64, 0x1,
>   	},
>   	/* SysMMU v7: Default register set (non-VM) */
>   	{
>   		0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x20, 0x24,
> -		0x60, 0x64,
> +		0x60, 0x64, 0x1,
>   	},
>   	/* SysMMU v7: VM capable register set */
>   	{
>   		0x00, 0x04, 0x08, 0x800c, 0x8010, 0x8014, 0x8018, 0x8020,
> -		0x8024, 0x60, 0x64,
> +		0x8024, 0x60, 0x64, 0x8000,
>   	},
>   };
>   
> @@ -567,6 +570,18 @@ static void __sysmmu_init_config(struct sysmmu_drvdata *data)
>   	sysmmu_write(data, IDX_CFG, cfg);
>   }
>   
> +static void __sysmmu_enable_vid(struct sysmmu_drvdata *data)
> +{
> +	u32 ctrl;
> +
> +	if (MMU_MAJ_VER(data->version) < 7 || !data->has_vcr)
> +		return;
> +
> +	ctrl = sysmmu_read(data, IDX_CTRL_VM);
> +	ctrl |= CTRL_VM_ENABLE | CTRL_VM_FAULT_MODE_STALL;
> +	sysmmu_write(data, IDX_CTRL_VM, ctrl);
> +}
> +
>   static void __sysmmu_enable(struct sysmmu_drvdata *data)
>   {
>   	unsigned long flags;
> @@ -577,6 +592,7 @@ static void __sysmmu_enable(struct sysmmu_drvdata *data)
>   	sysmmu_write(data, IDX_CTRL, CTRL_BLOCK);
>   	__sysmmu_init_config(data);
>   	__sysmmu_set_ptbase(data, data->pgtable);
> +	__sysmmu_enable_vid(data);
>   	sysmmu_write(data, IDX_CTRL, CTRL_ENABLE);
>   	data->active = true;
>   	spin_unlock_irqrestore(&data->lock, flags);

Best regards
diff mbox series

Patch

diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index 64bf3331064f..2b333e137f57 100644
--- a/drivers/iommu/exynos-iommu.c
+++ b/drivers/iommu/exynos-iommu.c
@@ -135,6 +135,8 @@  static u32 lv2ent_offset(sysmmu_iova_t iova)
 #define CFG_SYSSEL	(1 << 22) /* System MMU 3.2 only */
 #define CFG_FLPDCACHE	(1 << 20) /* System MMU 3.2+ only */
 
+#define CTRL_VM_ENABLE			BIT(0)
+#define CTRL_VM_FAULT_MODE_STALL	BIT(3)
 #define CAPA0_CAPA1_EXIST		BIT(11)
 #define CAPA1_VCR_ENABLED		BIT(14)
 
@@ -183,6 +185,7 @@  enum {
 	IDX_FLUSH_END,
 	IDX_INT_STATUS,
 	IDX_INT_CLEAR,
+	IDX_CTRL_VM,
 	MAX_REG_IDX
 };
 
@@ -196,22 +199,22 @@  static const unsigned int sysmmu_regs[MAX_REG_SET][MAX_REG_IDX] = {
 	/* SysMMU v1..v3 */
 	{
 		0x00, 0x04, 0x08, 0x14, 0x0c, 0x10, 0x1, 0x1, 0x1,
-		0x18, 0x1c,
+		0x18, 0x1c, 0x1,
 	},
 	/* SysMMU v5 */
 	{
 		0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x20, 0x24,
-		0x60, 0x64,
+		0x60, 0x64, 0x1,
 	},
 	/* SysMMU v7: Default register set (non-VM) */
 	{
 		0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x20, 0x24,
-		0x60, 0x64,
+		0x60, 0x64, 0x1,
 	},
 	/* SysMMU v7: VM capable register set */
 	{
 		0x00, 0x04, 0x08, 0x800c, 0x8010, 0x8014, 0x8018, 0x8020,
-		0x8024, 0x60, 0x64,
+		0x8024, 0x60, 0x64, 0x8000,
 	},
 };
 
@@ -567,6 +570,18 @@  static void __sysmmu_init_config(struct sysmmu_drvdata *data)
 	sysmmu_write(data, IDX_CFG, cfg);
 }
 
+static void __sysmmu_enable_vid(struct sysmmu_drvdata *data)
+{
+	u32 ctrl;
+
+	if (MMU_MAJ_VER(data->version) < 7 || !data->has_vcr)
+		return;
+
+	ctrl = sysmmu_read(data, IDX_CTRL_VM);
+	ctrl |= CTRL_VM_ENABLE | CTRL_VM_FAULT_MODE_STALL;
+	sysmmu_write(data, IDX_CTRL_VM, ctrl);
+}
+
 static void __sysmmu_enable(struct sysmmu_drvdata *data)
 {
 	unsigned long flags;
@@ -577,6 +592,7 @@  static void __sysmmu_enable(struct sysmmu_drvdata *data)
 	sysmmu_write(data, IDX_CTRL, CTRL_BLOCK);
 	__sysmmu_init_config(data);
 	__sysmmu_set_ptbase(data, data->pgtable);
+	__sysmmu_enable_vid(data);
 	sysmmu_write(data, IDX_CTRL, CTRL_ENABLE);
 	data->active = true;
 	spin_unlock_irqrestore(&data->lock, flags);