diff mbox series

[2/6] dt-bindings: clock: exynosautov9: add fsys1 clock definitions

Message ID 20220727060146.9228-3-chanho61.park@samsung.com (mailing list archive)
State New
Headers show
Series [1/6] dt-bindings: clk: exynosautov9: add fys0 clock definitions | expand

Commit Message

Chanho Park July 27, 2022, 6:01 a.m. UTC
Add fsys1(for usb and mmc) clock definitions.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
 .../dt-bindings/clock/samsung,exynosautov9.h  | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

Comments

Chanwoo Choi July 27, 2022, 7:38 a.m. UTC | #1
On 22. 7. 27. 15:01, Chanho Park wrote:
> Add fsys1(for usb and mmc) clock definitions.
> 
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
>  .../dt-bindings/clock/samsung,exynosautov9.h  | 25 +++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
> index 6305a84396ce..7e11e681da5c 100644
> --- a/include/dt-bindings/clock/samsung,exynosautov9.h
> +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
> @@ -228,6 +228,31 @@
>  
>  #define FSYS0_NR_CLK			37
>  
> +/* CMU_FSYS1 */
> +#define FOUT_MMC_PLL				1
> +
> +#define CLK_MOUT_FSYS1_BUS_USER			2
> +#define CLK_MOUT_MMC_PLL			3

nitpik. This clock id doesn't have 'FSYS1' word. Is it right?

> +#define CLK_MOUT_FSYS1_MMC_CARD_USER		4
> +#define CLK_MOUT_FSYS1_USBDRD_USER		5
> +#define CLK_MOUT_FSYS1_MMC_CARD			6
> +
> +#define CLK_DOUT_FSYS1_MMC_CARD			7
> +
> +#define CLK_GOUT_FSYS1_PCLK			8
> +#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN		9
> +#define CLK_GOUT_FSYS1_MMC_CARD_ACLK		10
> +#define CLK_GOUT_FSYS1_USB20DRD_0_REFCLK	11
> +#define CLK_GOUT_FSYS1_USB20DRD_1_REFCLK	12
> +#define CLK_GOUT_FSYS1_USB30DRD_0_REFCLK	13
> +#define CLK_GOUT_FSYS1_USB30DRD_1_REFCLK	14
> +#define CLK_GOUT_FSYS1_USB20_0_ACLK		15
> +#define CLK_GOUT_FSYS1_USB20_1_ACLK		16
> +#define CLK_GOUT_FSYS1_USB30_0_ACLK		17
> +#define CLK_GOUT_FSYS1_USB30_1_ACLK		18
> +
> +#define FSYS1_NR_CLK				19
> +
>  /* CMU_FSYS2 */
>  #define CLK_MOUT_FSYS2_BUS_USER		1
>  #define CLK_MOUT_FSYS2_UFS_EMBD_USER	2
Chanho Park July 27, 2022, 7:53 a.m. UTC | #2
> Subject: Re: [PATCH 2/6] dt-bindings: clock: exynosautov9: add fsys1 clock
> definitions
> 
> On 22. 7. 27. 15:01, Chanho Park wrote:
> > Add fsys1(for usb and mmc) clock definitions.
> >
> > Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> > ---
> >  .../dt-bindings/clock/samsung,exynosautov9.h  | 25 +++++++++++++++++++
> >  1 file changed, 25 insertions(+)
> >
> > diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h
> b/include/dt-bindings/clock/samsung,exynosautov9.h
> > index 6305a84396ce..7e11e681da5c 100644
> > --- a/include/dt-bindings/clock/samsung,exynosautov9.h
> > +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
> > @@ -228,6 +228,31 @@
> >
> >  #define FSYS0_NR_CLK			37
> >
> > +/* CMU_FSYS1 */
> > +#define FOUT_MMC_PLL				1
> > +
> > +#define CLK_MOUT_FSYS1_BUS_USER			2
> > +#define CLK_MOUT_MMC_PLL			3
> 
> nitpik. This clock id doesn't have 'FSYS1' word. Is it right?

Nice catch. I copied it from the SoC User manual but it should have the FSYS1 prefix because it's definitely included in the FSYS1 cmu block
I'll update it next patchset.

Best Regards,
Chanho Park
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
index 6305a84396ce..7e11e681da5c 100644
--- a/include/dt-bindings/clock/samsung,exynosautov9.h
+++ b/include/dt-bindings/clock/samsung,exynosautov9.h
@@ -228,6 +228,31 @@ 
 
 #define FSYS0_NR_CLK			37
 
+/* CMU_FSYS1 */
+#define FOUT_MMC_PLL				1
+
+#define CLK_MOUT_FSYS1_BUS_USER			2
+#define CLK_MOUT_MMC_PLL			3
+#define CLK_MOUT_FSYS1_MMC_CARD_USER		4
+#define CLK_MOUT_FSYS1_USBDRD_USER		5
+#define CLK_MOUT_FSYS1_MMC_CARD			6
+
+#define CLK_DOUT_FSYS1_MMC_CARD			7
+
+#define CLK_GOUT_FSYS1_PCLK			8
+#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN		9
+#define CLK_GOUT_FSYS1_MMC_CARD_ACLK		10
+#define CLK_GOUT_FSYS1_USB20DRD_0_REFCLK	11
+#define CLK_GOUT_FSYS1_USB20DRD_1_REFCLK	12
+#define CLK_GOUT_FSYS1_USB30DRD_0_REFCLK	13
+#define CLK_GOUT_FSYS1_USB30DRD_1_REFCLK	14
+#define CLK_GOUT_FSYS1_USB20_0_ACLK		15
+#define CLK_GOUT_FSYS1_USB20_1_ACLK		16
+#define CLK_GOUT_FSYS1_USB30_0_ACLK		17
+#define CLK_GOUT_FSYS1_USB30_1_ACLK		18
+
+#define FSYS1_NR_CLK				19
+
 /* CMU_FSYS2 */
 #define CLK_MOUT_FSYS2_BUS_USER		1
 #define CLK_MOUT_FSYS2_UFS_EMBD_USER	2