diff mbox series

arm64: dts: fsd: Change the reg properties from 64-bit to 32-bit

Message ID 20221116091247.52388-1-vivek.2311@samsung.com (mailing list archive)
State New
Headers show
Series arm64: dts: fsd: Change the reg properties from 64-bit to 32-bit | expand

Commit Message

Vivek Yadav Nov. 16, 2022, 9:12 a.m. UTC 
Change the reg properties from 64-bit to 32-bit for all IPs, as none of
the nodes are above 32-bit range in the fsd SoC.

Since dma-ranges length does not fit into 32-bit size, keep it 64-bit
and move it to specific node where it is used instead of SoC section.

Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Vivek Yadav <vivek.2311@samsung.com>
---
 arch/arm64/boot/dts/tesla/fsd-evb.dts |   2 +
 arch/arm64/boot/dts/tesla/fsd.dtsi    | 109 ++++++++++++++------------
 2 files changed, 62 insertions(+), 49 deletions(-)

Comments

Arnd Bergmann Nov. 16, 2022, 11:16 a.m. UTC | #1 
On Wed, Nov 16, 2022, at 10:12, Vivek Yadav wrote:
> Change the reg properties from 64-bit to 32-bit for all IPs, as none of
> the nodes are above 32-bit range in the fsd SoC.
>
> Since dma-ranges length does not fit into 32-bit size, keep it 64-bit
> and move it to specific node where it is used instead of SoC section.

I don't think that works, the dma-ranges property is part of the
bus, not a particular device:

 		mdma0: dma-controller@10100000 {
 			compatible = "arm,pl330", "arm,primecell";
-			reg = <0x0 0x10100000 0x0 0x1000>;
+			reg = <0x10100000 0x1000>;
 			interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
 			clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>;
 			clock-names = "apb_pclk";
 			iommus = <&smmu_imem 0x800 0x0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x0 0x0 0x10 0x0>;
 		};

Since the dma-controller has no children, I don't see how this has
any effect. Also, translating a 36-bit address into a 32-bit
address just means it gets truncated anyway, so there is no
point in making it appear to have a larger address range.

      Arnd
Robin Murphy Nov. 16, 2022, 12:38 p.m. UTC | #2 
On 2022-11-16 11:16, Arnd Bergmann wrote:
> On Wed, Nov 16, 2022, at 10:12, Vivek Yadav wrote:
>> Change the reg properties from 64-bit to 32-bit for all IPs, as none of
>> the nodes are above 32-bit range in the fsd SoC.
>>
>> Since dma-ranges length does not fit into 32-bit size, keep it 64-bit
>> and move it to specific node where it is used instead of SoC section.
> 
> I don't think that works, the dma-ranges property is part of the
> bus, not a particular device:
> 
>   		mdma0: dma-controller@10100000 {
>   			compatible = "arm,pl330", "arm,primecell";
> -			reg = <0x0 0x10100000 0x0 0x1000>;
> +			reg = <0x10100000 0x1000>;
>   			interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
>   			#dma-cells = <1>;
>   			clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>;
>   			clock-names = "apb_pclk";
>   			iommus = <&smmu_imem 0x800 0x0>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			dma-ranges = <0x0 0x0 0x0 0x10 0x0>;
>   		};
> 
> Since the dma-controller has no children, I don't see how this has
> any effect. Also, translating a 36-bit address into a 32-bit
> address just means it gets truncated anyway, so there is no
> point in making it appear to have a larger address range.

Yes, this is definitely bogus on both counts.

Thanks,
Robin.
Robin Murphy Nov. 16, 2022, 12:44 p.m. UTC | #3 
On 2022-11-16 12:38, Robin Murphy wrote:
> On 2022-11-16 11:16, Arnd Bergmann wrote:
>> On Wed, Nov 16, 2022, at 10:12, Vivek Yadav wrote:
>>> Change the reg properties from 64-bit to 32-bit for all IPs, as none of
>>> the nodes are above 32-bit range in the fsd SoC.
>>>
>>> Since dma-ranges length does not fit into 32-bit size, keep it 64-bit
>>> and move it to specific node where it is used instead of SoC section.
>>
>> I don't think that works, the dma-ranges property is part of the
>> bus, not a particular device:
>>
>>           mdma0: dma-controller@10100000 {
>>               compatible = "arm,pl330", "arm,primecell";
>> -            reg = <0x0 0x10100000 0x0 0x1000>;
>> +            reg = <0x10100000 0x1000>;
>>               interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
>>               #dma-cells = <1>;
>>               clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>;
>>               clock-names = "apb_pclk";
>>               iommus = <&smmu_imem 0x800 0x0>;
>> +            #address-cells = <2>;
>> +            #size-cells = <2>;
>> +            dma-ranges = <0x0 0x0 0x0 0x10 0x0>;
>>           };
>>
>> Since the dma-controller has no children, I don't see how this has
>> any effect. Also, translating a 36-bit address into a 32-bit
>> address just means it gets truncated anyway, so there is no
>> point in making it appear to have a larger address range.
> 
> Yes, this is definitely bogus on both counts.

Oh, and also that PL330 can only do 32-bit DMA anyway :)

Thanks,
Robin.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
index 1db6ddf03f01..81d9937d8828 100644
--- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
+++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
@@ -14,6 +14,8 @@ 
 / {
 	model = "Tesla Full Self-Driving (FSD) Evaluation board";
 	compatible = "tesla,fsd-evb", "tesla,fsd";
+	#address-cells = <2>;
+	#size-cells = <2>;
 
 	aliases {
 		serial0 = &serial_0;
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index f35bc5a288c2..7378ae39233a 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -342,23 +342,22 @@ 
 
 	soc: soc@0 {
 		compatible = "simple-bus";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>;
-		dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x0 0x18000000>;
 
 		gic: interrupt-controller@10400000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <3>;
 			interrupt-controller;
-			reg =	<0x0 0x10400000 0x0 0x10000>, /* GICD */
-				<0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */
+			reg =	<0x10400000 0x10000>, /* GICD */
+				<0x10600000 0x200000>; /* GICR_RD+GICR_SGI */
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
 		smmu_imem: iommu@10200000 {
 			compatible = "arm,mmu-500";
-			reg = <0x0 0x10200000 0x0 0x10000>;
+			reg = <0x10200000 0x10000>;
 			#iommu-cells = <2>;
 			#global-interrupts = <7>;
 			interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
@@ -378,7 +377,7 @@ 
 
 		smmu_isp: iommu@12100000 {
 			compatible = "arm,mmu-500";
-			reg = <0x0 0x12100000 0x0 0x10000>;
+			reg = <0x12100000 0x10000>;
 			#iommu-cells = <2>;
 			#global-interrupts = <11>;
 			interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
@@ -406,7 +405,7 @@ 
 
 		smmu_peric: iommu@14900000 {
 			compatible = "arm,mmu-500";
-			reg = <0x0 0x14900000 0x0 0x10000>;
+			reg = <0x14900000 0x10000>;
 			#iommu-cells = <2>;
 			#global-interrupts = <5>;
 			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
@@ -422,7 +421,7 @@ 
 
 		smmu_fsys0: iommu@15450000 {
 			compatible = "arm,mmu-500";
-			reg = <0x0 0x15450000 0x0 0x10000>;
+			reg = <0x15450000 0x10000>;
 			#iommu-cells = <2>;
 			#global-interrupts = <5>;
 			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
@@ -438,7 +437,7 @@ 
 
 		clock_imem: clock-controller@10010000 {
 			compatible = "tesla,fsd-clock-imem";
-			reg = <0x0 0x10010000 0x0 0x3000>;
+			reg = <0x10010000 0x3000>;
 			#clock-cells = <1>;
 			clocks = <&fin_pll>,
 				<&clock_cmu DOUT_CMU_IMEM_TCUCLK>,
@@ -452,7 +451,7 @@ 
 
 		clock_cmu: clock-controller@11c10000 {
 			compatible = "tesla,fsd-clock-cmu";
-			reg = <0x0 0x11c10000 0x0 0x3000>;
+			reg = <0x11c10000 0x3000>;
 			#clock-cells = <1>;
 			clocks = <&fin_pll>;
 			clock-names = "fin_pll";
@@ -460,7 +459,7 @@ 
 
 		clock_csi: clock-controller@12610000 {
 			compatible = "tesla,fsd-clock-cam_csi";
-			reg = <0x0 0x12610000 0x0 0x3000>;
+			reg = <0x12610000 0x3000>;
 			#clock-cells = <1>;
 			clocks = <&fin_pll>;
 			clock-names = "fin_pll";
@@ -468,7 +467,7 @@ 
 
 		clock_mfc: clock-controller@12810000 {
 			compatible = "tesla,fsd-clock-mfc";
-			reg = <0x0 0x12810000 0x0 0x3000>;
+			reg = <0x12810000 0x3000>;
 			#clock-cells = <1>;
 			clocks = <&fin_pll>;
 			clock-names = "fin_pll";
@@ -476,7 +475,7 @@ 
 
 		clock_peric: clock-controller@14010000 {
 			compatible = "tesla,fsd-clock-peric";
-			reg = <0x0 0x14010000 0x0 0x3000>;
+			reg = <0x14010000 0x3000>;
 			#clock-cells = <1>;
 			clocks = <&fin_pll>,
 				<&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>,
@@ -494,7 +493,7 @@ 
 
 		clock_fsys0: clock-controller@15010000 {
 			compatible = "tesla,fsd-clock-fsys0";
-			reg = <0x0 0x15010000 0x0 0x3000>;
+			reg = <0x15010000 0x3000>;
 			#clock-cells = <1>;
 			clocks = <&fin_pll>,
 				<&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>,
@@ -508,7 +507,7 @@ 
 
 		clock_fsys1: clock-controller@16810000 {
 			compatible = "tesla,fsd-clock-fsys1";
-			reg = <0x0 0x16810000 0x0 0x3000>;
+			reg = <0x16810000 0x3000>;
 			#clock-cells = <1>;
 			clocks = <&fin_pll>,
 				<&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
@@ -520,47 +519,59 @@ 
 
 		mdma0: dma-controller@10100000 {
 			compatible = "arm,pl330", "arm,primecell";
-			reg = <0x0 0x10100000 0x0 0x1000>;
+			reg = <0x10100000 0x1000>;
 			interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
 			clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>;
 			clock-names = "apb_pclk";
 			iommus = <&smmu_imem 0x800 0x0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x0 0x0 0x10 0x0>;
 		};
 
 		mdma1: dma-controller@10110000 {
 			compatible = "arm,pl330", "arm,primecell";
-			reg = <0x0 0x10110000 0x0 0x1000>;
+			reg = <0x10110000 0x1000>;
 			interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
 			clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>;
 			clock-names = "apb_pclk";
 			iommus = <&smmu_imem 0x801 0x0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x0 0x0 0x10 0x0>;
 		};
 
 		pdma0: dma-controller@14280000 {
 			compatible = "arm,pl330", "arm,primecell";
-			reg = <0x0 0x14280000 0x0 0x1000>;
+			reg = <0x14280000 0x1000>;
 			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
 			clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>;
 			clock-names = "apb_pclk";
 			iommus = <&smmu_peric 0x2 0x0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x0 0x0 0x10 0x0>;
 		};
 
 		pdma1: dma-controller@14290000 {
 			compatible = "arm,pl330", "arm,primecell";
-			reg = <0x0 0x14290000 0x0 0x1000>;
+			reg = <0x14290000 0x1000>;
 			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
 			clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>;
 			clock-names = "apb_pclk";
 			iommus = <&smmu_peric 0x1 0x0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			dma-ranges = <0x0 0x0 0x0 0x10 0x0>;
 		};
 
 		serial_0: serial@14180000 {
 			compatible = "samsung,exynos4210-uart";
-			reg = <0x0 0x14180000 0x0 0x100>;
+			reg = <0x14180000 0x100>;
 			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 			dmas = <&pdma1 1>, <&pdma1 0>;
 			dma-names = "rx", "tx";
@@ -572,7 +583,7 @@ 
 
 		serial_1: serial@14190000 {
 			compatible = "samsung,exynos4210-uart";
-			reg = <0x0 0x14190000 0x0 0x100>;
+			reg = <0x14190000 0x100>;
 			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 			dmas = <&pdma1 3>, <&pdma1 2>;
 			dma-names = "rx", "tx";
@@ -584,12 +595,12 @@ 
 
 		pmu_system_controller: system-controller@11400000 {
 			compatible = "samsung,exynos7-pmu", "syscon";
-			reg = <0x0 0x11400000 0x0 0x5000>;
+			reg = <0x11400000 0x5000>;
 		};
 
 		watchdog_0: watchdog@100a0000 {
 			compatible = "samsung,exynos7-wdt";
-			reg = <0x0 0x100a0000 0x0 0x100>;
+			reg = <0x100a0000 0x100>;
 			interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
 			samsung,syscon-phandle = <&pmu_system_controller>;
 			clocks = <&fin_pll>;
@@ -598,7 +609,7 @@ 
 
 		watchdog_1: watchdog@100b0000 {
 			compatible = "samsung,exynos7-wdt";
-			reg = <0x0 0x100b0000 0x0 0x100>;
+			reg = <0x100b0000 0x100>;
 			interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
 			samsung,syscon-phandle = <&pmu_system_controller>;
 			clocks = <&fin_pll>;
@@ -607,7 +618,7 @@ 
 
 		watchdog_2: watchdog@100c0000 {
 			compatible = "samsung,exynos7-wdt";
-			reg = <0x0 0x100c0000 0x0 0x100>;
+			reg = <0x100c0000 0x100>;
 			interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
 			samsung,syscon-phandle = <&pmu_system_controller>;
 			clocks = <&fin_pll>;
@@ -616,7 +627,7 @@ 
 
 		pwm_0: pwm@14100000 {
 			compatible = "samsung,exynos4210-pwm";
-			reg = <0x0 0x14100000 0x0 0x100>;
+			reg = <0x14100000 0x100>;
 			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 			#pwm-cells = <3>;
 			clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>;
@@ -626,7 +637,7 @@ 
 
 		pwm_1: pwm@14110000 {
 			compatible = "samsung,exynos4210-pwm";
-			reg = <0x0 0x14110000 0x0 0x100>;
+			reg = <0x14110000 0x100>;
 			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 			#pwm-cells = <3>;
 			clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>;
@@ -636,7 +647,7 @@ 
 
 		hsi2c_0: i2c@14200000 {
 			compatible = "samsung,exynos7-hsi2c";
-			reg = <0x0 0x14200000 0x0 0x1000>;
+			reg = <0x14200000 0x1000>;
 			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -649,7 +660,7 @@ 
 
 		hsi2c_1: i2c@14210000 {
 			compatible = "samsung,exynos7-hsi2c";
-			reg = <0x0 0x14210000 0x0 0x1000>;
+			reg = <0x14210000 0x1000>;
 			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -662,7 +673,7 @@ 
 
 		hsi2c_2: i2c@14220000 {
 			compatible = "samsung,exynos7-hsi2c";
-			reg = <0x0 0x14220000 0x0 0x1000>;
+			reg = <0x14220000 0x1000>;
 			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -675,7 +686,7 @@ 
 
 		hsi2c_3: i2c@14230000 {
 			compatible = "samsung,exynos7-hsi2c";
-			reg = <0x0 0x14230000 0x0 0x1000>;
+			reg = <0x14230000 0x1000>;
 			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -688,7 +699,7 @@ 
 
 		hsi2c_4: i2c@14240000 {
 			compatible = "samsung,exynos7-hsi2c";
-			reg = <0x0 0x14240000 0x0 0x1000>;
+			reg = <0x14240000 0x1000>;
 			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -701,7 +712,7 @@ 
 
 		hsi2c_5: i2c@14250000 {
 			compatible = "samsung,exynos7-hsi2c";
-			reg = <0x0 0x14250000 0x0 0x1000>;
+			reg = <0x14250000 0x1000>;
 			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -714,7 +725,7 @@ 
 
 		hsi2c_6: i2c@14260000 {
 			compatible = "samsung,exynos7-hsi2c";
-			reg = <0x0 0x14260000 0x0 0x1000>;
+			reg = <0x14260000 0x1000>;
 			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -727,7 +738,7 @@ 
 
 		hsi2c_7: i2c@14270000 {
 			compatible = "samsung,exynos7-hsi2c";
-			reg = <0x0 0x14270000 0x0 0x1000>;
+			reg = <0x14270000 0x1000>;
 			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -740,24 +751,24 @@ 
 
 		pinctrl_pmu: pinctrl@114f0000 {
 			compatible = "tesla,fsd-pinctrl";
-			reg = <0x0 0x114f0000 0x0 0x1000>;
+			reg = <0x114f0000 0x1000>;
 		};
 
 		pinctrl_peric: pinctrl@141f0000 {
 			compatible = "tesla,fsd-pinctrl";
-			reg = <0x0 0x141f0000 0x0 0x1000>;
+			reg = <0x141f0000 0x1000>;
 			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
 		pinctrl_fsys0: pinctrl@15020000 {
 			compatible = "tesla,fsd-pinctrl";
-			reg = <0x0 0x15020000 0x0 0x1000>;
+			reg = <0x15020000 0x1000>;
 			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
 		spi_0: spi@14140000 {
 			compatible = "tesla,fsd-spi";
-			reg = <0x0 0x14140000 0x0 0x100>;
+			reg = <0x14140000 0x100>;
 			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 			dmas = <&pdma1 4>, <&pdma1 5>;
 			dma-names = "tx", "rx";
@@ -775,7 +786,7 @@ 
 
 		spi_1: spi@14150000 {
 			compatible = "tesla,fsd-spi";
-			reg = <0x0 0x14150000 0x0 0x100>;
+			reg = <0x14150000 0x100>;
 			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 			dmas = <&pdma1 6>, <&pdma1 7>;
 			dma-names = "tx", "rx";
@@ -793,7 +804,7 @@ 
 
 		spi_2: spi@14160000 {
 			compatible = "tesla,fsd-spi";
-			reg = <0x0 0x14160000 0x0 0x100>;
+			reg = <0x14160000 0x100>;
 			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 			dmas = <&pdma1 8>, <&pdma1 9>;
 			dma-names = "tx", "rx";
@@ -811,7 +822,7 @@ 
 
 		timer@10040000 {
 			compatible = "tesla,fsd-mct", "samsung,exynos4210-mct";
-			reg = <0x0 0x10040000 0x0 0x800>;
+			reg = <0x10040000 0x800>;
 			interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
@@ -834,10 +845,10 @@ 
 
 		ufs: ufs@15120000 {
 			compatible = "tesla,fsd-ufs";
-			reg = <0x0 0x15120000 0x0 0x200>,  /* 0: HCI standard */
-			      <0x0 0x15121100 0x0 0x200>,  /* 1: Vendor specified */
-			      <0x0 0x15110000 0x0 0x8000>,  /* 2: UNIPRO */
-			      <0x0 0x15130000 0x0 0x100>;  /* 3: UFS protector */
+			reg = <0x15120000 0x200>,  /* 0: HCI standard */
+			      <0x15121100 0x200>,  /* 1: Vendor specified */
+			      <0x15110000 0x8000>,  /* 2: UNIPRO */
+			      <0x15130000 0x100>;  /* 3: UFS protector */
 			reg-names = "hci", "vs_hci", "unipro", "ufsp";
 			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>,
@@ -853,7 +864,7 @@ 
 
 		ufs_phy: ufs-phy@15124000 {
 			compatible = "tesla,fsd-ufs-phy";
-			reg = <0x0 0x15124000 0x0 0x800>;
+			reg = <0x15124000 0x800>;
 			reg-names = "phy-pma";
 			samsung,pmu-syscon = <&pmu_system_controller>;
 			#phy-cells = <0>;