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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id a11-20020ac25e6b000000b0048a9e899693sm1762826lfr.16.2022.12.04.03.38.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Dec 2022 03:38:43 -0800 (PST) From: Krzysztof Kozlowski To: Rob Herring , Krzysztof Kozlowski , Alim Akhtar , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH RFT 2/3] arm64: dts: exynos: drop clock-frequency from CPU nodes in TM2 Date: Sun, 4 Dec 2022 12:38:38 +0100 Message-Id: <20221204113839.151816-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221204113839.151816-1-krzysztof.kozlowski@linaro.org> References: <20221204113839.151816-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The CPU frequencies are determined by OPP table, so drop the 'clock-frequency' property. It is not parsed by any driver. Signed-off-by: Krzysztof Kozlowski --- "It is not parsed" - I hope... --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 8619920da4b6..88983d912479 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -89,7 +89,6 @@ cpu0: cpu@100 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x100>; - clock-frequency = <1300000000>; clocks = <&cmu_apollo CLK_SCLK_APOLLO>; clock-names = "apolloclk"; operating-points-v2 = <&cluster_a53_opp_table>; @@ -108,7 +107,6 @@ cpu1: cpu@101 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x101>; - clock-frequency = <1300000000>; operating-points-v2 = <&cluster_a53_opp_table>; #cooling-cells = <2>; i-cache-size = <0x8000>; @@ -125,7 +123,6 @@ cpu2: cpu@102 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x102>; - clock-frequency = <1300000000>; operating-points-v2 = <&cluster_a53_opp_table>; #cooling-cells = <2>; i-cache-size = <0x8000>; @@ -142,7 +139,6 @@ cpu3: cpu@103 { compatible = "arm,cortex-a53"; enable-method = "psci"; reg = <0x103>; - clock-frequency = <1300000000>; operating-points-v2 = <&cluster_a53_opp_table>; #cooling-cells = <2>; i-cache-size = <0x8000>; @@ -159,7 +155,6 @@ cpu4: cpu@0 { compatible = "arm,cortex-a57"; enable-method = "psci"; reg = <0x0>; - clock-frequency = <1900000000>; clocks = <&cmu_atlas CLK_SCLK_ATLAS>; clock-names = "atlasclk"; operating-points-v2 = <&cluster_a57_opp_table>; @@ -178,7 +173,6 @@ cpu5: cpu@1 { compatible = "arm,cortex-a57"; enable-method = "psci"; reg = <0x1>; - clock-frequency = <1900000000>; operating-points-v2 = <&cluster_a57_opp_table>; #cooling-cells = <2>; i-cache-size = <0xc000>; @@ -195,7 +189,6 @@ cpu6: cpu@2 { compatible = "arm,cortex-a57"; enable-method = "psci"; reg = <0x2>; - clock-frequency = <1900000000>; operating-points-v2 = <&cluster_a57_opp_table>; #cooling-cells = <2>; i-cache-size = <0xc000>; @@ -212,7 +205,6 @@ cpu7: cpu@3 { compatible = "arm,cortex-a57"; enable-method = "psci"; reg = <0x3>; - clock-frequency = <1900000000>; operating-points-v2 = <&cluster_a57_opp_table>; #cooling-cells = <2>; i-cache-size = <0xc000>;