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[92.12.225.146]) by smtp.gmail.com with ESMTPSA id t9-20020a5d4609000000b0031f8a59dbeasm2084336wrq.62.2023.10.05.08.57.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 08:57:35 -0700 (PDT) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, cw00.choi@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH 11/21] dt-bindings: clock: gs101: Add cmu_misc clock indices Date: Thu, 5 Oct 2023 16:56:08 +0100 Message-ID: <20231005155618.700312-12-peter.griffin@linaro.org> X-Mailer: git-send-email 2.42.0.582.g8ccd20d70d-goog In-Reply-To: <20231005155618.700312-1-peter.griffin@linaro.org> References: <20231005155618.700312-1-peter.griffin@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org CMU_MISC generates clocks for IPs such as Watchdog. Add clock indices for the PLLs, Muxes, dividers and gates in this clock management unit. Signed-off-by: Peter Griffin --- include/dt-bindings/clock/gs101.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/dt-bindings/clock/gs101.h b/include/dt-bindings/clock/gs101.h index d9b8299fcc0b..7765ba68f734 100644 --- a/include/dt-bindings/clock/gs101.h +++ b/include/dt-bindings/clock/gs101.h @@ -218,4 +218,15 @@ #define CLK_APM_PLL_DIV4_APM 13 #define CLK_APM_PLL_DIV16_APM 14 +/* CMU_MISC */ + +#define CLK_MOUT_MISC_BUS_USER 1 +#define CLK_MOUT_MISC_SSS_USER 2 +#define CLK_DOUT_MISC_BUSP 3 +#define CLK_DOUT_MISC_GIC 4 +#define CLK_GOUT_MISC_PCLK 5 +#define CLK_GOUT_MISC_SYSREG_PCLK 6 +#define CLK_GOUT_MISC_WDT_CLUSTER0 7 +#define CLK_GOUT_MISC_WDT_CLUSTER1 8 + #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */