[v4,13/19] pinctrl: samsung: Add gs101 SoC pinctrl configuration

Message ID	20231120212037.911774-14-peter.griffin@linaro.org (mailing list archive)
State	New
Headers	show Return-Path: <linux-samsung-soc-owner@vger.kernel.org> From: Peter Griffin <peter.griffin@linaro.org> To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, gregkh@linuxfoundation.org, jirislaby@kernel.org, cw00.choi@samsung.com, alim.akhtar@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, willmcvicker@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org Subject: [PATCH v4 13/19] pinctrl: samsung: Add gs101 SoC pinctrl configuration Date: Mon, 20 Nov 2023 21:20:31 +0000 Message-ID: <20231120212037.911774-14-peter.griffin@linaro.org> In-Reply-To: <20231120212037.911774-1-peter.griffin@linaro.org> References: <20231120212037.911774-1-peter.griffin@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board \| expand [v4,00/19] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board [v4,01/19] dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible [v4,02/19] dt-bindings: clock: Add Google gs101 clock management unit bindings [v4,03/19] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101 [v4,04/19] dt-bindings: watchdog: Document Google gs101 watchdog bindings [v4,05/19] dt-bindings: arm: google: Add bindings for Google ARM platforms [v4,06/19] dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible [v4,07/19] dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible [v4,08/19] dt-bindings: serial: samsung: Add google-gs101-uart compatible [v4,09/19] dt-bindings: serial: samsung: Make samsung,uart-fifosize required property [v4,10/19] clk: samsung: clk-pll: Add support for pll_{0516,0517,518} [v4,11/19] clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support [v4,12/19] pinctrl: samsung: Add filter selection support for alive banks [v4,13/19] pinctrl: samsung: Add gs101 SoC pinctrl configuration [v4,14/19] watchdog: s3c2410_wdt: Add support for Google gs101 SoC [v4,15/19] watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit [v4,16/19] tty: serial: samsung: Add gs101 compatible and common fifoszdt_serial_drv_data [v4,17/19] arm64: dts: exynos: google: Add initial Google gs101 SoC support [v4,18/19] arm64: dts: exynos: google: Add initial Oriole/pixel 6 board support [v4,19/19] MAINTAINERS: add entry for Google Tensor SoC

diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index cb965cf93705..e1a0668ecb16 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -796,3 +796,162 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { .ctrl = fsd_pin_ctrl, .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), }; + +/* + * bank type for non-alive type + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4) + * (CONPDN bit field: 2, PUDPDN bit field: 4) + */ +static struct samsung_pin_bank_type gs101_bank_type_off = { + .fld_width = { 4, 1, 4, 4, 2, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +/* + * bank type for alive type + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4) + */ +static const struct samsung_pin_bank_type gs101_bank_type_alive = { + .fld_width = { 4, 1, 4, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + +/* pin banks of gs101 pin-controller (ALIVE) */ +static const struct samsung_pin_bank_data gs101_pin_alive[] = { + EXYNOS9_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08, 0x10), + EXYNOS9_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c, 0x18), + EXYNOS9_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10, 0x1c), + EXYNOS9_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14, 0x20), + EXYNOS9_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18, 0x28), + EXYNOS9_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c, 0x30), +}; + +/* pin banks of gs101 pin-controller (FAR_ALIVE) */ +static const struct samsung_pin_bank_data gs101_pin_far_alive[] = { + EXYNOS9_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08, 0x0c), + EXYNOS9_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c, 0x14), +}; + +/* pin banks of gs101 pin-controller (GSACORE) */ +static const struct samsung_pin_bank_data gs101_pin_gsacore[] = { + EXYNOS9_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08, 0x0c), +}; + +/* pin banks of gs101 pin-controller (GSACTRL) */ +static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = { + EXYNOS9_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00, 0x00), +}; + +/* pin banks of gs101 pin-controller (PERIC0) */ +static const struct samsung_pin_bank_data gs101_pin_peric0[] = { + EXYNOS9_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08, 0x0c), + EXYNOS9_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c, 0x10), + EXYNOS9_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10, 0x14), + EXYNOS9_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14, 0x18), + EXYNOS9_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18, 0x1c), + EXYNOS9_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c, 0x20), + EXYNOS9_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20, 0x24), + EXYNOS9_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24, 0x28), + EXYNOS9_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28, 0x2c), + EXYNOS9_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c, 0x30), + EXYNOS9_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30, 0x34), + EXYNOS9_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34, 0x38), + EXYNOS9_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38, 0x3c), + EXYNOS9_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c, 0x40), + EXYNOS9_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40, 0x44), + EXYNOS9_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44, 0x48), + EXYNOS9_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48, 0x4c), + EXYNOS9_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c, 0x50), +}; + +/* pin banks of gs101 pin-controller (PERIC1) */ +static const struct samsung_pin_bank_data gs101_pin_peric1[] = { + EXYNOS9_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08, 0x0c), + EXYNOS9_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c, 0x10), + EXYNOS9_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10, 0x18), + EXYNOS9_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14, 0x1c), + EXYNOS9_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18, 0x20), + EXYNOS9_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c, 0x28), +}; + +/* pin banks of gs101 pin-controller (HSI1) */ +static const struct samsung_pin_bank_data gs101_pin_hsi1[] = { + EXYNOS9_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04, 0x08), +}; + +/* pin banks of gs101 pin-controller (HSI2) */ +static const struct samsung_pin_bank_data gs101_pin_hsi2[] = { + EXYNOS9_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08, 0x0c), +}; + +static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { + { + /* pin banks of gs101 pin-controller (ALIVE) */ + .pin_banks = gs101_pin_alive, + .nr_banks = ARRAY_SIZE(gs101_pin_alive), + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin banks of gs101 pin-controller (FAR_ALIVE) */ + .pin_banks = gs101_pin_far_alive, + .nr_banks = ARRAY_SIZE(gs101_pin_far_alive), + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin banks of gs101 pin-controller (GSACORE) */ + .pin_banks = gs101_pin_gsacore, + .nr_banks = ARRAY_SIZE(gs101_pin_gsacore), + }, { + /* pin banks of gs101 pin-controller (GSACTRL) */ + .pin_banks = gs101_pin_gsactrl, + .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl), + }, { + /* pin banks of gs101 pin-controller (PERIC0) */ + .pin_banks = gs101_pin_peric0, + .nr_banks = ARRAY_SIZE(gs101_pin_peric0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin banks of gs101 pin-controller (PERIC1) */ + .pin_banks = gs101_pin_peric1, + .nr_banks = ARRAY_SIZE(gs101_pin_peric1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin banks of gs101 pin-controller (HSI1) */ + .pin_banks = gs101_pin_hsi1, + .nr_banks = ARRAY_SIZE(gs101_pin_hsi1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin banks of gs101 pin-controller (HSI2) */ + .pin_banks = gs101_pin_hsi2, + .nr_banks = ARRAY_SIZE(gs101_pin_hsi2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = { + .ctrl = gs101_pin_ctrl, + .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 56fc11a1fe2f..75b9cf72ce73 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -537,6 +537,8 @@ static const struct of_device_id exynos_wkup_irq_ids[] = { .data = &exynos7_wkup_irq_chip }, { .compatible = "samsung,exynosautov9-wakeup-eint", .data = &exynos7_wkup_irq_chip }, + { .compatible = "google,gs101-wakeup-eint", + .data = &exynos7_wkup_irq_chip }, { } }; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index e2799ff1b5e9..1ffc90db079d 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -147,6 +147,40 @@ .name = id \ } +#define EXYNOS9_PIN_BANK_EINTN(types, pins, reg, id) \ + { \ + .type = &types, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .fltcon_type = FLT_DEFAULT \ + .name = id \ + } + +#define EXYNOS9_PIN_BANK_EINTG(pins, reg, id, offs, fltcon_offs) \ + { \ + .type = &gs101_bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .fltcon_type = FLT_DEFAULT, \ + .fltcon_offset = fltcon_offs, \ + .name = id \ + } + +#define EXYNOS9_PIN_BANK_EINTW(pins, reg, id, offs, fltcon_offs) \ + { \ + .type = &gs101_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .fltcon_type = FLT_SELECTABLE, \ + .fltcon_offset = fltcon_offs, \ + .name = id \ + } + /** * struct exynos_weint_data: irq specific data for all the wakeup interrupts * generated by the external wakeup interrupt controller. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 50c360b4753a..982a5702714c 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1323,6 +1323,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynosautov9_of_data }, { .compatible = "tesla,fsd-pinctrl", .data = &fsd_of_data }, + { .compatible = "google,gs101-pinctrl", + .data = &gs101_of_data }, #endif #ifdef CONFIG_PINCTRL_S3C64XX { .compatible = "samsung,s3c64xx-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 5fab3885a7d7..f6856290608c 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -373,6 +373,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; extern const struct samsung_pinctrl_of_match_data fsd_of_data; +extern const struct samsung_pinctrl_of_match_data gs101_of_data; extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;

[v4,13/19] pinctrl: samsung: Add gs101 SoC pinctrl configuration

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