From patchwork Sat Feb 24 20:20:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 13570605 Received: from mail-ot1-f51.google.com (mail-ot1-f51.google.com [209.85.210.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 302D54CDEB for ; Sat, 24 Feb 2024 20:20:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708806057; cv=none; b=AMOF/taFeQUoJlHIHWNVjc/Q83hbh2ygAF63oQr15V5yZmXGreEv///CkjpD0hxOo8S2Q3xUGi1k5ynixWbbE4p9u2XzHDE6ME8xc1Jh0kwc+f5GlDV2i19D+WA/a90rTF0eEhF4nVtU8TDuFExfGTtFDk+ncltcv4YoqaCT9f4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708806057; c=relaxed/simple; bh=OhURSWM8+fuAVHhkszMUOwGry5e3K6VMP6vMpX968h0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=U89M+FGZYm5TDNFuD+ps4Se24MuDw0AdS7yX8EaKsRVLVbwjtSktYYX/0pwBQO99Da7SwulWY3WsZo7iIygPg+WZVLrv/0GwBDA24gNYIuq5Kfe+vj7E3zvadimAsNBFoLKdINtMuZt2GMi2qYroFTXDhg62vwcv/p3NldVMsiY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=LXnOPI4w; arc=none smtp.client-ip=209.85.210.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="LXnOPI4w" Received: by mail-ot1-f51.google.com with SMTP id 46e09a7af769-6ddca59e336so1161137a34.0 for ; Sat, 24 Feb 2024 12:20:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708806055; x=1709410855; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Itgu/CZdB2adz5dOihNeRA11oIiQNAIilHhTarLaGhY=; b=LXnOPI4wcHhWM0iUeHs2bGAvvsTSoMWPV00HsLUebi738YVCJHAIbdZPa27epBlW1T iycZvEqmpyGGIlaqExYN4Uol46DbTwjef3kpCZ0uEEe2hzulxN/7aYiimL5rV9oyNPyg kdAQK8qfo69VGLnCcbkdHwm5vYX75JzZoOilUblVDFFbBCcl4WCTdo4SoFbieCjGTnVe qi9LyH3ICfGtkUUh6RVuNu2YhGm8JZHGcq0Ph0BRgWHWiDLr7GiV0RoiTarYN3g4bXJS Uye3RM69rR4wcPzazDOTwL0Csb76AskY2F+O+RFpqu7CEWZzu7zsbp/hmEQu7YYkY6b4 bw+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708806055; x=1709410855; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Itgu/CZdB2adz5dOihNeRA11oIiQNAIilHhTarLaGhY=; b=LUvmjsjFrbZ6U1ormPBPbGxzhP3LkoRq4fqccamoC7qcXoB7TZcLaL5hxzFtAN88Au pSRZyX3T92jzXp7uPH1djvf6P/oK4mBY1jGTAd1kIFmfhzPq1pitPeHVU7m/5n8h2WWH BZk3RonbRH8LVH4sLlIVVYP41z1Ky+3F1x0gKN/2cQsyfdRzPBWBTuBvnC2IJcbuxajO Qz9BSiiHOcSVkECLI6KnPmUi8UR29Ytpo3B5S8gWnNx052JrpiDg73X9rmRe5vr0q2X5 H2crDg9cLx9YsJdzAYn2c0aPzAZsPjwF/OfeqQ0YG7oLb0bDx8npQDhlKFXo8Q/7LUye JZAg== X-Forwarded-Encrypted: i=1; AJvYcCUD0WcbqnjjRw9EVg9vKD8w9baRkm3sTr36N/7VM/M/W8Ag+Gsta6Bqj+d2+hgiA9231T2Xej/RMOBQL1NvLITCtCPodMaYdIBE7urfdAgc6y4= X-Gm-Message-State: AOJu0YzHWHi6uJ9VibcTbaZaWZkhSR/51RejniY2anGcseA2cXhU9NU/ FS8m9ev0WdlJXm6UWfrjgWer/CQkgbtg91JZmrMa9uPx2f/wMeJHTpYV59WR22A= X-Google-Smtp-Source: AGHT+IEaFdafQDxvOhqf7szlKBjLkGDFQh1IaD2JJ1F/oKaL+attengEbCt1ufEL8VF8J7YfxLkw5w== X-Received: by 2002:a9d:6045:0:b0:6e4:8c95:1ac9 with SMTP id v5-20020a9d6045000000b006e48c951ac9mr1050906otj.16.1708806055136; Sat, 24 Feb 2024 12:20:55 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id m24-20020a4a2418000000b005a044f901c0sm454345oof.23.2024.02.24.12.20.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Feb 2024 12:20:54 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi Cc: Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Tomasz Figa , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 01/15] dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1 Date: Sat, 24 Feb 2024 14:20:39 -0600 Message-Id: <20240224202053.25313-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240224202053.25313-1-semen.protsenko@linaro.org> References: <20240224202053.25313-1-semen.protsenko@linaro.org> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document CPU clock management unit compatibles and add corresponding clock indices. Exynos850 has two CPU clusters (CL0 and CL1), each containing 4 Cortex-A55 cores. CPU PLLs are generating main CPU clocks for each cluster, and there are alternate ("switch") clocks that can be used temporarily while re-configuring the PLL for the new rate. ACLK, ATCLK, PCLKDBG and PERIPHCLK clocks are driving corresponding buses. CLK_CLUSTERx_SCLK are actual leaf CPU clocks and should be used to change CPU rates. Also some CoreSight clocks can be derived from DBG_USER (debug clock). Signed-off-by: Sam Protsenko --- Changes in v3: - none Changes in v2: - none .../clock/samsung,exynos850-clock.yaml | 42 +++++++++++++++ include/dt-bindings/clock/exynos850.h | 54 +++++++++++++++++++ 2 files changed, 96 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml index c752c8985a53..cdc5ded59fe5 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml @@ -36,6 +36,8 @@ properties: - samsung,exynos850-cmu-aud - samsung,exynos850-cmu-cmgp - samsung,exynos850-cmu-core + - samsung,exynos850-cmu-cpucl0 + - samsung,exynos850-cmu-cpucl1 - samsung,exynos850-cmu-dpu - samsung,exynos850-cmu-g3d - samsung,exynos850-cmu-hsi @@ -152,6 +154,46 @@ allOf: - const: dout_core_mmc_embd - const: dout_core_sss + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-cpucl0 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CPUCL0 switch clock (from CMU_TOP) + - description: CPUCL0 debug clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cpucl0_switch + - const: dout_cpucl0_dbg + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-cpucl1 + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CPUCL1 switch clock (from CMU_TOP) + - description: CPUCL1 debug clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cpucl1_switch + - const: dout_cpucl1_dbg + - if: properties: compatible: diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h index bc15108aa3c2..7666241520f8 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -88,6 +88,18 @@ #define CLK_MOUT_G3D_SWITCH 76 #define CLK_GOUT_G3D_SWITCH 77 #define CLK_DOUT_G3D_SWITCH 78 +#define CLK_MOUT_CPUCL0_DBG 79 +#define CLK_MOUT_CPUCL0_SWITCH 80 +#define CLK_GOUT_CPUCL0_DBG 81 +#define CLK_GOUT_CPUCL0_SWITCH 82 +#define CLK_DOUT_CPUCL0_DBG 83 +#define CLK_DOUT_CPUCL0_SWITCH 84 +#define CLK_MOUT_CPUCL1_DBG 85 +#define CLK_MOUT_CPUCL1_SWITCH 86 +#define CLK_GOUT_CPUCL1_DBG 87 +#define CLK_GOUT_CPUCL1_SWITCH 88 +#define CLK_DOUT_CPUCL1_DBG 89 +#define CLK_DOUT_CPUCL1_SWITCH 90 /* CMU_APM */ #define CLK_RCO_I3C_PMIC 1 @@ -195,6 +207,48 @@ #define CLK_GOUT_CMGP_USI1_PCLK 14 #define CLK_GOUT_SYSREG_CMGP_PCLK 15 +/* CMU_CPUCL0 */ +#define CLK_FOUT_CPUCL0_PLL 1 +#define CLK_MOUT_PLL_CPUCL0 2 +#define CLK_MOUT_CPUCL0_SWITCH_USER 3 +#define CLK_MOUT_CPUCL0_DBG_USER 4 +#define CLK_MOUT_CPUCL0_PLL 5 +#define CLK_DOUT_CPUCL0_CPU 6 +#define CLK_DOUT_CPUCL0_CMUREF 7 +#define CLK_DOUT_CPUCL0_PCLK 8 +#define CLK_DOUT_CLUSTER0_ACLK 9 +#define CLK_DOUT_CLUSTER0_ATCLK 10 +#define CLK_DOUT_CLUSTER0_PCLKDBG 11 +#define CLK_DOUT_CLUSTER0_PERIPHCLK 12 +#define CLK_GOUT_CLUSTER0_ATCLK 13 +#define CLK_GOUT_CLUSTER0_PCLK 14 +#define CLK_GOUT_CLUSTER0_PERIPHCLK 15 +#define CLK_GOUT_CLUSTER0_SCLK 16 +#define CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK 17 +#define CLK_GOUT_CLUSTER0_CPU 18 +#define CLK_CLUSTER0_SCLK 19 + +/* CMU_CPUCL1 */ +#define CLK_FOUT_CPUCL1_PLL 1 +#define CLK_MOUT_PLL_CPUCL1 2 +#define CLK_MOUT_CPUCL1_SWITCH_USER 3 +#define CLK_MOUT_CPUCL1_DBG_USER 4 +#define CLK_MOUT_CPUCL1_PLL 5 +#define CLK_DOUT_CPUCL1_CPU 6 +#define CLK_DOUT_CPUCL1_CMUREF 7 +#define CLK_DOUT_CPUCL1_PCLK 8 +#define CLK_DOUT_CLUSTER1_ACLK 9 +#define CLK_DOUT_CLUSTER1_ATCLK 10 +#define CLK_DOUT_CLUSTER1_PCLKDBG 11 +#define CLK_DOUT_CLUSTER1_PERIPHCLK 12 +#define CLK_GOUT_CLUSTER1_ATCLK 13 +#define CLK_GOUT_CLUSTER1_PCLK 14 +#define CLK_GOUT_CLUSTER1_PERIPHCLK 15 +#define CLK_GOUT_CLUSTER1_SCLK 16 +#define CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK 17 +#define CLK_GOUT_CLUSTER1_CPU 18 +#define CLK_CLUSTER1_SCLK 19 + /* CMU_G3D */ #define CLK_FOUT_G3D_PLL 1 #define CLK_MOUT_G3D_PLL 2